Searched refs:Cyclone (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64.td | 47 /// Cyclone has register move instructions which are "free".
51 /// Cyclone has instructions which zero registers for "free".
204 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
205 "Cyclone", [
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| D | AArch64SchedCyclone.td | 1 //=- AArch64SchedCyclone.td - Cyclone Scheduling Definitions -*- tablegen -*-=//
10 // This file defines the machine model for AArch64 Cyclone to support
24 // Define each kind of processor resource and number available on Cyclone.
95 // Define scheduler read/write resources and latency on Cyclone.
243 def : SchedAlias<WriteLDIdx, CyWriteLDIdx>; // Map AArch64->Cyclone type.
249 def : SchedAlias<WriteSTIdx, CyWriteSTIdx>; // Map AArch64->Cyclone type.
257 def : SchedAlias<ReadAdrBase, CyReadAdrBase>; // Map AArch64->Cyclone type.
305 // Define some longer latency vector op types for Cyclone.
318 // TODO: Add Cyclone-specific zero-cycle zeros. LLVM currently
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| D | AArch64Subtarget.cpp | 56 case Cyclone: in initializeProperties()
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| D | AArch64Subtarget.h | 44 Cyclone, enumerator
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| D | AArch64SystemOperands.td | 1015 // Cyclone specific system registers
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| /external/llvm/test/CodeGen/ARM/ |
| D | zero-cycle-zero.ll | 51 ; crafted behaviour that we might break in Cyclone.
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| /external/llvm/test/CodeGen/AArch64/ |
| D | merge-store.ll | 26 ; On Cyclone, the stores should not get merged into a 16-byte store because
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| /external/llvm/lib/Target/ARM/ |
| D | ARM.td | 104 // Cyclone has preferred instructions for zeroing VFP registers, which can
797 // Cyclone is very similar to swift
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