/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrAtomics.td | 48 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm, 50 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>; 63 def : Pat<(relaxed_load<atomic_load_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm, 65 (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>; 78 def : Pat<(relaxed_load<atomic_load_32> (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm, 80 (LDRWroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)>; 93 def : Pat<(relaxed_load<atomic_load_64> (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm, 95 (LDRXroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>; 135 (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend), 137 (STRBBroX GPR32:$val, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend)>; [all …]
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D | AArch64InstrInfo.td | 333 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr), 334 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>, 340 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 341 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi), 345 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 346 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi), 350 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 351 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi), 355 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 356 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi), [all …]
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D | AArch64RegisterInfo.td | 129 // GPR64/GPR64sp for use by the coalescer. 144 def GPR64 : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR)> { 145 let AltOrders = [(rotl GPR64, 8)]; 191 def GPR64pi1 : RegisterOperand<GPR64, "printPostIncOperand<1>">; 192 def GPR64pi2 : RegisterOperand<GPR64, "printPostIncOperand<2>">; 193 def GPR64pi3 : RegisterOperand<GPR64, "printPostIncOperand<3>">; 194 def GPR64pi4 : RegisterOperand<GPR64, "printPostIncOperand<4>">; 195 def GPR64pi6 : RegisterOperand<GPR64, "printPostIncOperand<6>">; 196 def GPR64pi8 : RegisterOperand<GPR64, "printPostIncOperand<8>">; 197 def GPR64pi12 : RegisterOperand<GPR64, "printPostIncOperand<12>">; [all …]
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D | AArch64InstrFormats.td | 592 def arith_shifted_reg64 : arith_shifted_reg<i64, GPR64, 64>; 614 def logical_shifted_reg64 : logical_shifted_reg<i64, GPR64, logical_shift64>; 930 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg), 939 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt), 1014 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt), 1029 (ins GPR64:$Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2), 1063 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> { 1147 def X : BaseCmpBranch<GPR64, op, asm, node> { 1219 def X : BaseTestBranch<GPR64, tbz_imm32_63, op, asm, node> { 1227 def : Pat<(node GPR64:$Rn, tbz_imm0_31_diag:$imm, bb:$target), [all …]
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/external/llvm/test/CodeGen/Mips/ |
D | divrem.ll | 6 …ify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,GPR64-TRAP 13 …mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,NOCHECK 20 ; GPR64 - Same as GPR32 but only for 64-bit targets 24 ; GPR64-TRAP - Same as TRAP and GPR64 combined 43 ; GPR64: div $2, $4, $5 44 ; GPR64-TRAP: teq $5, $zero, 7 70 ; GPR64: mod $2, $4, $5 71 ; GPR64-TRAP: teq $5, $zero, 7 97 ; GPR64: divu $2, $4, $5 98 ; GPR64-TRAP: teq $5, $zero, 7 [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
D | SystemZRegisterInfo.td | 29 // GPR64 - One of the 16 64-bit general-purpose registers 30 class GPR64<bits<4> num, string n, list<Register> subregs, 82 def R0D : GPR64< 0, "r0", [R0W]>, DwarfRegNum<[0]>; 83 def R1D : GPR64< 1, "r1", [R1W]>, DwarfRegNum<[1]>; 84 def R2D : GPR64< 2, "r2", [R2W]>, DwarfRegNum<[2]>; 85 def R3D : GPR64< 3, "r3", [R3W]>, DwarfRegNum<[3]>; 86 def R4D : GPR64< 4, "r4", [R4W]>, DwarfRegNum<[4]>; 87 def R5D : GPR64< 5, "r5", [R5W]>, DwarfRegNum<[5]>; 88 def R6D : GPR64< 6, "r6", [R6W]>, DwarfRegNum<[6]>; 89 def R7D : GPR64< 7, "r7", [R7W]>, DwarfRegNum<[7]>; [all …]
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/external/llvm/lib/Target/Mips/ |
D | Mips64InstrInfo.td | 74 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>; 75 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>; 76 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>; 77 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>; 78 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>; 79 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>; 80 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>; 81 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>; 281 def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>, 283 def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>, [all …]
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D | MicroMips64r6InstrInfo.td | 436 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)), 437 (DADDIU_MM64R6 GPR64:$hi, tglobaladdr:$lo)>, ISA_MICROMIPS64R6; 438 def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)), 439 (DADDIU_MM64R6 GPR64:$hi, tblockaddress:$lo)>, ISA_MICROMIPS64R6; 440 def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)), 441 (DADDIU_MM64R6 GPR64:$hi, tjumptable:$lo)>, ISA_MICROMIPS64R6; 442 def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)), 443 (DADDIU_MM64R6 GPR64:$hi, tconstpool:$lo)>, ISA_MICROMIPS64R6; 444 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)), 445 (DADDIU_MM64R6 GPR64:$hi, tglobaltlsaddr:$lo)>, ISA_MICROMIPS64R6; [all …]
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D | MipsCondMov.td | 204 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>, 206 defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>, 208 defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>, 210 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>, 212 defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>, 214 defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>, 216 defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>, 218 defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>, 220 defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>, 225 defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, [all …]
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D | MipsRegisterInfo.td | 319 def GPR64 : RegisterClass<"Mips", [i64], 64, (add 567 def GPR64Opnd : RegisterOperand<GPR64> {
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D | MipsInstrInfo.td | 1953 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff, 1954 GPR64:$dst), 1955 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
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D | MipsMSAInstrInfo.td | 3774 GPR64), [HasMSA, IsGP64bit]>; 3795 GPR64), [HasMSA, IsGP64bit]>; 3843 GPR64), [HasMSA, IsGP64bit]>; 3880 GPR64),
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/external/llvm/test/CodeGen/Mips/llvm-ir/ |
D | ret.ll | 15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C 116 ; GPR64-DAG: daddiu $2, $[[T0]], 1 131 ; GPR64-DAG: daddiu $[[T1:[0-9]+]], $[[T0]], 1 132 ; GPR64-DAG: dsll $2, $[[T1]], 32 147 ; GPR64-DAG: ori $[[T0:[0-9]+]], $zero, 32769 [all …]
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZRegisterInfo.td | 63 class GPR64<bits<16> num, string n, GPR32 low, GPR32 high> 70 class GPR128<bits<16> num, string n, GPR64 low, GPR64 high> 80 def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L"), !cast<GPR32>("R"#I#"H")>, 85 def R#I#Q : GPR128<I, "r"#I, !cast<GPR64>("R"#!add(I, 1)#"D"), 86 !cast<GPR64>("R"#I#"D")>;
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D | SystemZFrameLowering.cpp | 119 unsigned GPR64, bool IsImplicit) { in addSavedGPR() argument 122 unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32); in addSavedGPR() 123 bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32); in addSavedGPR() 125 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive)); in addSavedGPR() 127 MBB.addLiveIn(GPR64); in addSavedGPR()
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-dead-register-def-bug.ll | 6 ; E.g. %X1<def, dead> = MOVi64imm 2, %W1<imp-def>; %X1:GPR64, %W1:GPR32
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86RegisterInfo.cpp | 431 const unsigned GPR64[] = { in getReservedRegs() local 435 for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI) in getReservedRegs()
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