/external/libunwind/src/x86_64/ |
D | Gstep.c | 135 c->dwarf.loc[RIP] = DWARF_LOC (c->dwarf.cfa, 0); in unw_step() 199 c->dwarf.loc[RIP] = rip_loc; in unw_step() 202 c->dwarf.ret_addr_column = RIP; in unw_step() 210 if (!DWARF_IS_NULL_LOC (c->dwarf.loc[RIP])) in unw_step() 212 ret = dwarf_get (&c->dwarf, c->dwarf.loc[RIP], &c->dwarf.ip); in unw_step() 214 (unsigned long long) DWARF_GET_LOC (c->dwarf.loc[RIP]), in unw_step()
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D | init.h | 65 c->dwarf.loc[RIP] = REG_INIT_LOC(c, rip, RIP); in common_init() 67 ret = dwarf_get (&c->dwarf, c->dwarf.loc[RIP], &c->dwarf.ip); in common_init() 80 c->dwarf.ret_addr_column = RIP; in common_init()
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D | Gos-freebsd.c | 127 c->dwarf.loc[RIP] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RIP, 0); in unw_handle_signal_frame() 136 c->dwarf.loc[RIP] = DWARF_LOC (c->dwarf.cfa, 0); in unw_handle_signal_frame() 137 ret = dwarf_get (&c->dwarf, c->dwarf.loc[RIP], &c->dwarf.ip); in unw_handle_signal_frame() 139 (unsigned long long) DWARF_GET_LOC (c->dwarf.loc[RIP]), in unw_handle_signal_frame()
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D | unwind_i.h | 55 #define RIP 16 macro
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D | Gregs.c | 78 loc = c->dwarf.loc[RIP]; in tdep_access_reg()
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D | Gstash_frame.c | 87 assert (DWARF_GET_LOC(d->loc[RIP]) - uc == UC_MCONTEXT_GREGS_RIP); in tdep_stash_frame()
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/external/llvm/lib/Target/X86/ |
D | X86RegisterInfo.td | 148 def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>; 345 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since 346 // RIP isn't really a register and it can't be used anywhere except in an 350 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>; 376 R8, R9, R11, RIP)>; 378 R8, R9, R10, R11, RIP)>; 396 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>; 406 // GR64_NOSP - GR64 registers except RSP (and RIP). 407 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>; 421 // In such cases, it is fine to use RIP as we are sure the 32 high [all …]
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D | X86RegisterInfo.cpp | 51 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), in X86RegisterInfo() 54 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { in X86RegisterInfo() 442 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid(); in getReservedRegs() 521 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP}) in adjustStackMapLiveOutMask()
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/external/valgrind/memcheck/tests/amd64-linux/ |
D | int3-amd64.stdout.exp | 2 in int_handler, RIP is ...
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/external/llvm/test/CodeGen/X86/ |
D | 2010-05-12-FastAllocKills.ll | 9 ; %reg1025<def> = MUL_Fp80m32 %reg1024, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool] 20 ; %FP2<def> = MUL_Fp80m32 %FP1, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
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D | ipra-reg-usage.ll | 6 ; CHECK: foo Clobbered Registers: CS DS EFLAGS EIP EIZ ES FPSW FS GS IP RIP RIZ SS BND0 BND1 BND2 B…
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/external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
D | 2010-05-12-FastAllocKills.ll | 9 ; %reg1025<def> = MUL_Fp80m32 %reg1024, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool] 20 ; %FP2<def> = MUL_Fp80m32 %FP1, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
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/external/strace/linux/x86_64/ |
D | userent.h | 17 XLAT(8*RIP),
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86RegisterInfo.td | 143 def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>; 309 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since 310 // RIP isn't really a register and it can't be used anywhere except in an 314 RBX, R14, R15, R12, R13, RBP, RSP, RIP)> { 357 R8, R9, R11, RIP)> { 387 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)> { 405 // GR64_NOSP - GR64 registers except RSP (and RIP). 406 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)> {
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D | X86CodeEmitter.cpp | 474 if (BaseReg == X86::RIP || in emitMemModRMByte() 493 if (BaseReg != 0 && BaseReg != X86::RIP) in emitMemModRMByte() 506 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode in emitMemModRMByte()
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D | X86GenRegisterInfo.inc | 130 RIP = 111, 298 const unsigned EIP_Overlaps[] = { X86::EIP, X86::IP, X86::RIP, 0 }; 312 const unsigned IP_Overlaps[] = { X86::IP, X86::EIP, X86::RIP, 0 }; 359 const unsigned RIP_Overlaps[] = { X86::RIP, X86::EIP, X86::IP, 0 }; 514 const unsigned EIP_SuperRegsSet[] = { X86::RIP, 0 }; 517 const unsigned IP_SuperRegsSet[] = { X86::EIP, X86::RIP, 0 }; 676 { "RIP", RIP_Overlaps, RIP_SubRegsSet, Empty_SuperRegsSet }, 740 …86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP, 860 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, 870 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP, [all …]
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/external/kernel-headers/original/uapi/asm-x86/asm/ |
D | ptrace-abi.h | 54 #define RIP 128 macro
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/external/llvm/lib/Analysis/ |
D | RegionPrinter.cpp | 146 static RegionInfo *getGraph(RegionInfoPass *RIP) { in getGraph() 147 return &RIP->getRegionInfo(); in getGraph()
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/X86/ |
D | enhanced.txt | 3 # CHECK: [o:jne][w: ][0-p:-][0-l:10=10] <br> 0:[RIP/111](pc)=18446744073709551606
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/external/valgrind/coregrind/m_sigframe/ |
D | sigframe-amd64-darwin.c | 109 SC2(__rip,RIP); in synthesize_ucontext() 137 SC2(RIP,__rip); in restore_from_ucontext()
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/external/google-breakpad/src/common/android/ |
D | breakpad_getcontext_unittest.cc | 137 CHECK_REG(RIP); in TEST()
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/external/llvm/lib/Transforms/ObjCARC/ |
D | ObjCARCOpts.cpp | 1606 for (Instruction *RIP : NewRetainReleaseRRI.ReverseInsertPts) { in PairUpRetainsAndReleases() 1607 if (ReleasesToMove.ReverseInsertPts.insert(RIP).second) { in PairUpRetainsAndReleases() 1610 const BBState &RIPBBState = BBStates[RIP->getParent()]; in PairUpRetainsAndReleases() 1663 for (Instruction *RIP : NewReleaseRetainRRI.ReverseInsertPts) { in PairUpRetainsAndReleases() 1664 if (RetainsToMove.ReverseInsertPts.insert(RIP).second) { in PairUpRetainsAndReleases() 1667 const BBState &RIPBBState = BBStates[RIP->getParent()]; in PairUpRetainsAndReleases()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
D | X86MCTargetDesc.cpp | 289 ? X86::RIP // Should have dwarf #16. in createX86MCRegisterInfo() 327 MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP); in createX86MCAsmInfo()
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
D | X86MCTargetDesc.cpp | 148 ? X86::RIP // Should have dwarf #16. in createX86MCRegisterInfo() 193 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; in createX86MCAsmInfo()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
D | X86DisassemblerDecoder.h | 291 ENTRY(RIP)
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