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Searched refs:RIP (Results 1 – 25 of 65) sorted by relevance

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/external/libunwind/src/x86_64/
DGstep.c135 c->dwarf.loc[RIP] = DWARF_LOC (c->dwarf.cfa, 0); in unw_step()
199 c->dwarf.loc[RIP] = rip_loc; in unw_step()
202 c->dwarf.ret_addr_column = RIP; in unw_step()
210 if (!DWARF_IS_NULL_LOC (c->dwarf.loc[RIP])) in unw_step()
212 ret = dwarf_get (&c->dwarf, c->dwarf.loc[RIP], &c->dwarf.ip); in unw_step()
214 (unsigned long long) DWARF_GET_LOC (c->dwarf.loc[RIP]), in unw_step()
Dinit.h65 c->dwarf.loc[RIP] = REG_INIT_LOC(c, rip, RIP); in common_init()
67 ret = dwarf_get (&c->dwarf, c->dwarf.loc[RIP], &c->dwarf.ip); in common_init()
80 c->dwarf.ret_addr_column = RIP; in common_init()
DGos-freebsd.c127 c->dwarf.loc[RIP] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RIP, 0); in unw_handle_signal_frame()
136 c->dwarf.loc[RIP] = DWARF_LOC (c->dwarf.cfa, 0); in unw_handle_signal_frame()
137 ret = dwarf_get (&c->dwarf, c->dwarf.loc[RIP], &c->dwarf.ip); in unw_handle_signal_frame()
139 (unsigned long long) DWARF_GET_LOC (c->dwarf.loc[RIP]), in unw_handle_signal_frame()
Dunwind_i.h55 #define RIP 16 macro
DGregs.c78 loc = c->dwarf.loc[RIP]; in tdep_access_reg()
DGstash_frame.c87 assert (DWARF_GET_LOC(d->loc[RIP]) - uc == UC_MCONTEXT_GREGS_RIP); in tdep_stash_frame()
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td148 def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>;
345 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
346 // RIP isn't really a register and it can't be used anywhere except in an
350 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
376 R8, R9, R11, RIP)>;
378 R8, R9, R10, R11, RIP)>;
396 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
406 // GR64_NOSP - GR64 registers except RSP (and RIP).
407 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
421 // In such cases, it is fine to use RIP as we are sure the 32 high
[all …]
DX86RegisterInfo.cpp51 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), in X86RegisterInfo()
54 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { in X86RegisterInfo()
442 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid(); in getReservedRegs()
521 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP}) in adjustStackMapLiveOutMask()
/external/valgrind/memcheck/tests/amd64-linux/
Dint3-amd64.stdout.exp2 in int_handler, RIP is ...
/external/llvm/test/CodeGen/X86/
D2010-05-12-FastAllocKills.ll9 ; %reg1025<def> = MUL_Fp80m32 %reg1024, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
20 ; %FP2<def> = MUL_Fp80m32 %FP1, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
Dipra-reg-usage.ll6 ; CHECK: foo Clobbered Registers: CS DS EFLAGS EIP EIZ ES FPSW FS GS IP RIP RIZ SS BND0 BND1 BND2 B…
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
D2010-05-12-FastAllocKills.ll9 ; %reg1025<def> = MUL_Fp80m32 %reg1024, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
20 ; %FP2<def> = MUL_Fp80m32 %FP1, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
/external/strace/linux/x86_64/
Duserent.h17 XLAT(8*RIP),
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.td143 def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
309 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
310 // RIP isn't really a register and it can't be used anywhere except in an
314 RBX, R14, R15, R12, R13, RBP, RSP, RIP)> {
357 R8, R9, R11, RIP)> {
387 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)> {
405 // GR64_NOSP - GR64 registers except RSP (and RIP).
406 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)> {
DX86CodeEmitter.cpp474 if (BaseReg == X86::RIP || in emitMemModRMByte()
493 if (BaseReg != 0 && BaseReg != X86::RIP) in emitMemModRMByte()
506 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode in emitMemModRMByte()
DX86GenRegisterInfo.inc130 RIP = 111,
298 const unsigned EIP_Overlaps[] = { X86::EIP, X86::IP, X86::RIP, 0 };
312 const unsigned IP_Overlaps[] = { X86::IP, X86::EIP, X86::RIP, 0 };
359 const unsigned RIP_Overlaps[] = { X86::RIP, X86::EIP, X86::IP, 0 };
514 const unsigned EIP_SuperRegsSet[] = { X86::RIP, 0 };
517 const unsigned IP_SuperRegsSet[] = { X86::EIP, X86::RIP, 0 };
676 { "RIP", RIP_Overlaps, RIP_SubRegsSet, Empty_SuperRegsSet },
740 …86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
860 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP,
870 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP,
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/external/kernel-headers/original/uapi/asm-x86/asm/
Dptrace-abi.h54 #define RIP 128 macro
/external/llvm/lib/Analysis/
DRegionPrinter.cpp146 static RegionInfo *getGraph(RegionInfoPass *RIP) { in getGraph()
147 return &RIP->getRegionInfo(); in getGraph()
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/X86/
Denhanced.txt3 # CHECK: [o:jne][w: ][0-p:-][0-l:10=10] <br> 0:[RIP/111](pc)=18446744073709551606
/external/valgrind/coregrind/m_sigframe/
Dsigframe-amd64-darwin.c109 SC2(__rip,RIP); in synthesize_ucontext()
137 SC2(RIP,__rip); in restore_from_ucontext()
/external/google-breakpad/src/common/android/
Dbreakpad_getcontext_unittest.cc137 CHECK_REG(RIP); in TEST()
/external/llvm/lib/Transforms/ObjCARC/
DObjCARCOpts.cpp1606 for (Instruction *RIP : NewRetainReleaseRRI.ReverseInsertPts) { in PairUpRetainsAndReleases()
1607 if (ReleasesToMove.ReverseInsertPts.insert(RIP).second) { in PairUpRetainsAndReleases()
1610 const BBState &RIPBBState = BBStates[RIP->getParent()]; in PairUpRetainsAndReleases()
1663 for (Instruction *RIP : NewReleaseRetainRRI.ReverseInsertPts) { in PairUpRetainsAndReleases()
1664 if (RetainsToMove.ReverseInsertPts.insert(RIP).second) { in PairUpRetainsAndReleases()
1667 const BBState &RIPBBState = BBStates[RIP->getParent()]; in PairUpRetainsAndReleases()
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp289 ? X86::RIP // Should have dwarf #16. in createX86MCRegisterInfo()
327 MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP); in createX86MCAsmInfo()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp148 ? X86::RIP // Should have dwarf #16. in createX86MCRegisterInfo()
193 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; in createX86MCAsmInfo()
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h291 ENTRY(RIP)

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