/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMRegisterInfo.td | 29 def ssub_0 : SubRegIndex; 30 def ssub_1 : SubRegIndex; 31 def ssub_2 : SubRegIndex; // In a Q reg. 32 def ssub_3 : SubRegIndex; 34 def dsub_0 : SubRegIndex; 35 def dsub_1 : SubRegIndex; 36 def dsub_2 : SubRegIndex; 37 def dsub_3 : SubRegIndex; 38 def dsub_4 : SubRegIndex; 39 def dsub_5 : SubRegIndex; [all …]
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/external/llvm/lib/Target/AArch64/ |
D | AArch64RegisterInfo.td | 23 def sub_32 : SubRegIndex<32>; 25 def bsub : SubRegIndex<8>; 26 def hsub : SubRegIndex<16>; 27 def ssub : SubRegIndex<32>; 28 def dsub : SubRegIndex<32>; 29 def sube32 : SubRegIndex<32>; 30 def subo32 : SubRegIndex<32>; 31 def qhisub : SubRegIndex<64>; 32 def qsub : SubRegIndex<64>; 33 def sube64 : SubRegIndex<64>; [all …]
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/external/llvm/lib/Target/AMDGPU/ |
D | R600ExpandSpecialInstrs.cpp | 286 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction() local 287 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction() 288 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction() 301 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction() local 302 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
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D | AMDGPURegisterInfo.td | 17 def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
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/external/llvm/lib/Target/PowerPC/ |
D | PPCQPXLoadSplat.cpp | 108 unsigned SubRegIndex = in runOnMachineFunction() local 110 unsigned SplatSubReg = TRI->getSubReg(SplatReg, SubRegIndex); in runOnMachineFunction()
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D | PPCRegisterInfo.td | 14 def sub_lt : SubRegIndex<1>; 15 def sub_gt : SubRegIndex<1, 1>; 16 def sub_eq : SubRegIndex<1, 2>; 17 def sub_un : SubRegIndex<1, 3>; 18 def sub_32 : SubRegIndex<32>; 19 def sub_64 : SubRegIndex<64>; 20 def sub_128 : SubRegIndex<128>;
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZRegisterInfo.td | 24 def subreg_l32 : SubRegIndex<32, 0>; // Also acts as subreg_ll32. 25 def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_lh32. 26 def subreg_l64 : SubRegIndex<64, 0>; 27 def subreg_h64 : SubRegIndex<64, 64>; 28 def subreg_r32 : SubRegIndex<32, 32>; // Reinterpret a wider reg as 32 bits. 29 def subreg_r64 : SubRegIndex<64, 64>; // Reinterpret a wider reg as 64 bits.
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/external/llvm/lib/Target/ARM/ |
D | ARMRegisterInfo.td | 30 def qqsub_0 : SubRegIndex<256>; 31 def qqsub_1 : SubRegIndex<256, 256>; 34 def qsub_0 : SubRegIndex<128>; 35 def qsub_1 : SubRegIndex<128, 128>; 39 def dsub_0 : SubRegIndex<64>; 40 def dsub_1 : SubRegIndex<64, 64>; 48 def ssub_0 : SubRegIndex<32>; 49 def ssub_1 : SubRegIndex<32, 32>; 53 def gsub_0 : SubRegIndex<32>; 54 def gsub_1 : SubRegIndex<32, 32>;
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/external/llvm/lib/Target/Mips/ |
D | MipsRegisterInfo.td | 14 def sub_32 : SubRegIndex<32>; 15 def sub_64 : SubRegIndex<64>; 16 def sub_lo : SubRegIndex<32>; 17 def sub_hi : SubRegIndex<32, 32>; 18 def sub_dsp16_19 : SubRegIndex<4, 16>; 19 def sub_dsp20 : SubRegIndex<1, 20>; 20 def sub_dsp21 : SubRegIndex<1, 21>; 21 def sub_dsp22 : SubRegIndex<1, 22>; 22 def sub_dsp23 : SubRegIndex<1, 23>;
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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
D | SystemZRegisterInfo.td | 57 def subreg_32bit : SubRegIndex; 58 def subreg_odd32 : SubRegIndex; 59 def subreg_even : SubRegIndex; 60 def subreg_odd : SubRegIndex;
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86RegisterInfo.td | 22 def sub_8bit : SubRegIndex; 23 def sub_8bit_hi : SubRegIndex; 24 def sub_16bit : SubRegIndex; 25 def sub_32bit : SubRegIndex; 27 def sub_ss : SubRegIndex; 28 def sub_sd : SubRegIndex; 29 def sub_xmm : SubRegIndex;
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCRegisterInfo.td | 14 def sub_lt : SubRegIndex; 15 def sub_gt : SubRegIndex; 16 def sub_eq : SubRegIndex; 17 def sub_un : SubRegIndex; 18 def sub_32 : SubRegIndex;
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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
D | BlackfinRegisterInfo.td | 19 def lo16 : SubRegIndex; 20 def hi16 : SubRegIndex; 21 def lo32 : SubRegIndex; 22 def hi32 : SubRegIndex;
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/external/llvm/include/llvm/Target/ |
D | Target.td | 24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25 class SubRegIndex<int size, int offset = 0> { 37 // ComposedOf - A list of two SubRegIndex instances, [A, B]. 38 // This indicates that this SubRegIndex is the result of composing A and B. 40 list<SubRegIndex> ComposedOf = []; 56 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with 58 list<SubRegIndex> CoveringSubRegIndices = []; 63 class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B> 64 : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1, 67 // See SubRegIndex. [all …]
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/external/llvm/lib/CodeGen/ |
D | TargetRegisterInfo.cpp | 395 TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex, in dumpReg() argument 397 dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n"; in dumpReg()
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/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
D | SparcRegisterInfo.td | 24 def sub_even : SubRegIndex; 25 def sub_odd : SubRegIndex;
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/external/llvm/lib/Target/X86/ |
D | X86RegisterInfo.td | 24 def sub_8bit : SubRegIndex<8>; 25 def sub_8bit_hi : SubRegIndex<8, 8>; 26 def sub_16bit : SubRegIndex<16>; 27 def sub_32bit : SubRegIndex<32>; 28 def sub_xmm : SubRegIndex<128>; 29 def sub_ymm : SubRegIndex<256>;
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/external/llvm/lib/Target/Lanai/ |
D | LanaiRegisterInfo.td | 22 def sub_32 : SubRegIndex<32>;
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
D | MipsRegisterInfo.td | 14 def sub_fpeven : SubRegIndex; 15 def sub_fpodd : SubRegIndex; 16 def sub_32 : SubRegIndex;
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonRegisterInfo.td | 84 def subreg_loreg : SubRegIndex<32>; 85 def subreg_hireg : SubRegIndex<32, 32>; 86 def subreg_overflow : SubRegIndex<1, 0>;
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/external/llvm/lib/Target/Sparc/ |
D | SparcRegisterInfo.td | 25 def sub_even : SubRegIndex<32>; 26 def sub_odd : SubRegIndex<32, 32>; 27 def sub_even64 : SubRegIndex<64>; 28 def sub_odd64 : SubRegIndex<64, 64>;
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/external/swiftshader/third_party/LLVM/include/llvm/Target/ |
D | Target.td | 24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25 class SubRegIndex { 54 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 57 list<SubRegIndex> SubRegIndices = []; 145 // dags: (RegClass SubRegIndex, SubRegindex, ...) 226 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> { 232 // SubRegIndices - N SubRegIndex instances. This provides the names of the 234 list<SubRegIndex> SubRegIndices = Indices;
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/external/llvm/lib/Target/AVR/ |
D | AVRRegisterInfo.td | 32 def sub_lo : SubRegIndex<8>; 33 def sub_hi : SubRegIndex<8, 8>;
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/external/llvm/lib/Target/MSP430/ |
D | MSP430RegisterInfo.td | 46 def subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; }
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/external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
D | MSP430RegisterInfo.td | 46 def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; }
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