/external/llvm/lib/Target/AArch64/ |
D | AArch64SystemOperands.td | 41 def : AT<"S1E0R", 0b01, 0b000, 0b0111, 0b1000, 0b010>; 96 def : DC<"ISW", 0b01, 0b000, 0b0111, 0b0110, 0b010>; 98 def : DC<"CSW", 0b01, 0b000, 0b0111, 0b1010, 0b010>; 101 def : DC<"CISW", 0b01, 0b000, 0b0111, 0b1110, 0b010>; 239 def : TLBI<"ASIDE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b010>; 255 def : TLBI<"ASIDE1", 0b01, 0b000, 0b1000, 0b0111, 0b010>; 329 def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>; 337 def : ROSysReg<"ID_ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b010>; 351 def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010> { 356 def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>; [all …]
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D | AArch64InstrInfo.td | 388 def : InstAlias<"wfe", (HINT 0b010)>; 399 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">; 797 def SMULHrr : MulHi<0b010, "smulh", mulhs>; 840 defm LDEOR : LDOPregister<0b010, "eor", 0, 0, "">; 841 defm LDEORA : LDOPregister<0b010, "eor", 1, 0, "a">; 842 defm LDEORL : LDOPregister<0b010, "eor", 0, 1, "l">; 843 defm LDEORAL : LDOPregister<0b010, "eor", 1, 1, "al">; 973 def REVWr : OneWRegData<0b010, "rev", bswap>; 975 def REV32Xr : OneXRegData<0b010, "rev32", 1279 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">; [all …]
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D | AArch64InstrFormats.td | 1515 let Inst{15-13} = 0b010; 3209 let Inst{25-23} = 0b010; 5242 def v4i32_v4i16 : BaseSIMDDifferentThreeVector<U, 0b010, opc, 5304 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc, 5337 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc, 5377 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc, 5416 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc, 5451 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc, 5479 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc, 5520 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc, [all …]
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonInstrInfo.td | 193 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>; 880 def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>; 895 def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>; 896 def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>; 897 def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>; 903 def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>; 904 def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>; 905 def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>; 906 def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>; 909 def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>; [all …]
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D | HexagonInstrInfoVector.td | 75 def S2_asr_i_vw : vshift_v2i32<sra, "vasrw", 0b010, 0b000>; 76 def S2_lsr_i_vw : vshift_v2i32<srl, "vlsrw", 0b010, 0b001>; 77 def S2_asl_i_vw : vshift_v2i32<shl, "vaslw", 0b010, 0b010>; 81 def S2_asl_i_vh : vshift_v4i16<shl, "vaslh", 0b100, 0b010>;
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D | HexagonInstrInfoV5.td | 34 def M5_vmpybsu: T_XTYPE_mpy64 <"vmpybsu", 0b010, 0b001, 0, 0, 0>; 174 def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>; 274 def F2_dfcmpge : T_fcmp64<"dfcmp.ge", setoge, 0b010>; 614 def F2_conv_d2sf : F2_RD_RSS_CONVERT <"convert_d2sf", 0b010, 620 def F2_conv_w2sf : F2_RD_RS_CONVERT <"convert_w2sf", 0b010, 0b000, 624 def F2_conv_ud2df : F2_RDD_RSS_CONVERT <"convert_ud2df", 0b010, 628 def F2_conv_w2df : F2_RDD_RS_CONVERT <"convert_w2df", 0b010,
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D | HexagonInstrInfoV4.td | 140 def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>; 187 def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>; 621 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>; 714 def S4_storerh_ap : T_ST_absset <"memh", "STrih", IntRegs, 0b010, 789 def S4_storerh_ur : T_StoreAbsReg <"memh", "STrih", IntRegs, 0b010, 1024 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>, 1626 defm J4_cmpgtu : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel; 1686 defm J4_cmpgtui : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel; 1978 def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>; 1983 def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>; [all …]
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D | HexagonSystemInst.td | 74 "l2fetch($Rs, $Rt)", [], 0b011, 0b010, 0b0>;
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D | HexagonIsetDx.td | 592 let Inst{12-10} = 0b010;
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/external/llvm/lib/Target/Mips/ |
D | MipsMSAInstrInfo.td | 407 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>; 408 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>; 409 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>; 410 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>; 569 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>; 570 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>; 571 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>; 572 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>; 579 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>; 580 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>; [all …]
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D | Mips32r6InstrFormats.td | 450 let Inst{10-8} = 0b010;
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/external/swiftshader/third_party/LLVM/test/TableGen/ |
D | if.td | 10 let n{8-6} = !if(x{2}, 0b010, 0b110);
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/external/mesa3d/src/compiler/glsl/tests/ |
D | array_refcount_test.cpp | 671 operand b010 = deref_array( in TEST_F() local 685 deref_array(var_b, b010), in TEST_F()
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/external/llvm/test/TableGen/ |
D | if.td | 17 let n{8-6} = !if(x{2}, 0b010, 0b110);
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/external/llvm/lib/Target/Sparc/ |
D | SparcInstr64Bit.td | 369 defm BPLEZ : BranchOnReg<0b010, "brlez">; 394 defm MOVRLEZ : MOVR<0b010, "movrlez">; 419 defm FMOVRLEZ : FMOVR<0b010, "lez">;
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D | SparcInstrInfo.td | 769 : F2_2<0b010, 0, (outs), ins, asmstr, pattern> { 784 : F2_2<0b010, 0, (outs), ins, asmstr, pattern, IIC_iu_instr>; 788 : F2_2<0b010, 1, (outs), ins, asmstr, pattern, IIC_iu_instr>;
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
D | brw_disasm.c | 353 [0b010] = "OWord Dual Block Read", 363 [0b010] = "media block write", 418 [0b010] = "SIMD8/DualSrcLow",
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/external/llvm/lib/Target/Lanai/ |
D | LanaiInstrInfo.td | 319 defm SUB_ : ALUarith<0b010, "sub", sub, i32lo16z, i32hi16>; 351 defm SUB_F_ : ALUarith<0b010, "sub.f", subc, i32lo16z, i32hi16>; 724 defm SFSUB_F : SF<0b010, "sub.f">; 824 def LEADZ: InstSpecial<0b010, (outs GPR:$Rd), (ins GPR:$Rs1),
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D | LanaiInstrFormats.td | 538 // 0b010 LEADZ Count number of leading zeros;
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 1785 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">; 1791 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">; 1897 let Inst{26-24} = 0b010; 1899 let Inst{22-20} = 0b010; 1935 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">; 1948 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">; 1955 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">; 1961 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">; 1970 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">; 1976 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">; [all …]
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D | ARMInstrInfo.td | 1408 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1438 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr), 1468 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1497 def i12 : AI2ldst<0b010, 0, isByte, (outs), 2166 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 4504 let Inst{23-21} = 0b010; 4530 let Inst{23-21} = 0b010;
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 1975 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">; 1981 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">; 2102 let Inst{26-24} = 0b010; 2104 let Inst{22-20} = 0b010; 2140 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">; 2153 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">; 2160 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">; 2166 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">; 2175 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">; 2181 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">; [all …]
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D | ARMInstrInfo.td | 1730 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1760 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 1792 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1821 def i12 : AI2ldst<0b010, 0, isByte, (outs), 2509 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 5121 let Inst{23-21} = 0b010; 5152 let Inst{23-21} = 0b010;
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/external/llvm/lib/Target/AVR/ |
D | AVRInstrInfo.td | 1015 0b010, 1022 0b010,
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/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
D | SparcInstrInfo.td | 507 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> {
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