Home
last modified time | relevance | path

Searched refs:getInstr (Results 1 – 25 of 45) sorted by relevance

12

/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp30 if (SUnits[su].getInstr()->isCall()) in postprocessDAG()
33 else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall) in postprocessDAG()
44 if (!SU || !SU->getInstr()) in isResourceAvailable()
49 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
51 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
101 switch (SU->getInstr()->getOpcode()) { in reserveResources()
103 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
124 DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
249 assert(SU->getInstr() && "Scheduled SUnit must have instr"); in releaseBottomNode()
281 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard()
[all …]
DHexagonVLIWPacketizer.cpp382 if (PacketSU->getInstr()->isInlineAsm()) in canPromoteToDotCur()
553 if (PacketSU->getInstr()->mayStore()) in canPromoteToNewValueStore()
639 MachineInstr* TempMI = TempSU->getInstr(); in canPromoteToNewValueStore()
652 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI)) in canPromoteToNewValueStore()
704 MachineInstr *PacketMI = PacketSU->getInstr(); in canPromoteToNewValue()
735 const MachineInstr *PI = PacketSU->getInstr(); in canPromoteToDotNew()
1136 MachineInstr *I = SUI->getInstr(); in isLegalToPacketizeTogether()
1137 MachineInstr *J = SUJ->getInstr(); in isLegalToPacketizeTogether()
1179 MachineInstr *PI = PacketSU->getInstr(); in isLegalToPacketizeTogether()
1448 MachineInstr *I = SUI->getInstr(); in isLegalToPruneDependencies()
[all …]
/external/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp163 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
164 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
198 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
223 MachineInstr *MI = SU->getInstr(); in getAluKind()
296 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
325 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
327 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { in PopInst()
396 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
445 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
DGCNHazardRecognizer.cpp34 EmitInstruction(SU->getInstr()); in EmitInstruction()
43 MachineInstr *MI = SU->getInstr(); in getHazardType()
58 return PreEmitNoops(SU->getInstr()); in PreEmitNoops()
DSIMachineScheduler.cpp251 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure); in pickNode()
318 RPTracker.setPos(SU->getInstr()); in initRegPressure()
399 TopRPTracker.setPos(SU->getInstr()); in schedule()
1205 MachineInstr *MI = SU->getInstr(); in scheduleInsideBlocks()
1234 Block->schedule((*SUs.begin())->getInstr(), (*SUs.rbegin())->getInstr()); in scheduleInsideBlocks()
1697 if (SITII->isLowLatencyInstruction(*Pred->getInstr())) { in moveLowLatencies()
1707 if (SITII->isLowLatencyInstruction(*SU->getInstr())) { in moveLowLatencies()
1728 } else if (SU->getInstr()->getOpcode() == AMDGPU::COPY) { in moveLowLatencies()
1732 if (SITII->isLowLatencyInstruction(*Succ->getInstr())) { in moveLowLatencies()
1817 if (SITII->isLowLatencyInstruction(*SU->getInstr())) { in schedule()
[all …]
DR600Packetizer.cpp186 MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr(); in isLegalToPacketizeTogether()
DSILoadStoreOptimizer.cpp284 return Read2.getInstr(); in mergeRead2Pair()
361 return Write2.getInstr(); in mergeWrite2Pair()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DScheduleDAGInstrs.cpp281 !DefSU->getInstr()->registerDefIsDead(Reg))) in BuildSchedGraph()
292 !DefSU->getInstr()->registerDefIsDead(*Alias))) in BuildSchedGraph()
313 MachineInstr *UseMI = UseSU->getInstr(); in BuildSchedGraph()
579 if (SU->getInstr()->getDesc().mayLoad()) in ComputeLatency()
582 SU->Latency = TII->getInstrLatency(InstrItins, SU->getInstr()); in ComputeLatency()
599 MachineInstr *DefMI = Def->getInstr(); in ComputeOperandLatency()
613 MachineInstr *UseMI = Use->getInstr(); in ComputeOperandLatency()
644 SU->getInstr()->dump(); in dumpNode()
655 SU->getInstr()->print(oss); in getGraphNodeLabel()
676 BB->insert(InsertPos, SU->getInstr()); in EmitSchedule()
[all …]
DSlotIndexes.cpp154 if (itr->getInstr() != 0) { in dump()
155 dbgs() << *itr->getInstr(); in dump()
DCriticalAntiDepBreaker.cpp436 MISUnitMap[SU->getInstr()] = SU; in BreakAntiDependencies()
457 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr(); in BreakAntiDependencies()
562 CriticalPathMI = CriticalPathSU->getInstr(); in BreakAntiDependencies()
/external/llvm/lib/CodeGen/
DMachinePipeliner.cpp295 return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI(); in isBackedge()
302 return (!Source->getInstr()->isPHI() && in isOrder()
303 !Dep.getSUnit()->getInstr()->isPHI()); in isOrder()
313 if (Source->getInstr()->isPHI()) in getLatency()
315 if (Dep.getSUnit()->getInstr()->isPHI()) in getLatency()
327 if (V->getInstr()->isPHI() && Dep.getKind() == SDep::Anti) in getDistance()
515 os << " SU(" << I->NodeNum << ") " << *(I->getInstr()); in print()
999 MachineInstr &MI = *SU.getInstr(); in addLoopCarriedDependences()
1020 MachineInstr &LdMI = *Load->getInstr(); in addLoopCarriedDependences()
1085 MachineInstr *MI = I.getInstr(); in updatePhiDependences()
[all …]
DScheduleDAGInstrs.cpp284 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
311 RegUse = UseSU->getInstr(); in addPhysRegDataDeps()
314 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse, in addPhysRegDataDeps()
327 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
347 !DefSU->getInstr()->registerDefIsDead(*Alias))) { in addPhysRegDeps()
353 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
422 MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
460 MachineInstr *Use = UseSU->getInstr(); in addVRegDefDeps()
506 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addVRegDefDeps()
531 const MachineInstr *MI = SU->getInstr(); in addVRegUseDeps()
[all …]
DMachineScheduler.cpp712 MachineInstr *MI = SU->getInstr(); in schedule()
1015 << ' ' << *SU.getInstr(); in updatePressureDiffs()
1046 LI.Query(LIS->getInstructionIndex(*SU->getInstr())); in updatePressureDiffs()
1052 << *SU->getInstr(); in updatePressureDiffs()
1233 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(*SU->getInstr())); in computeCyclicCriticalPath()
1275 MachineInstr *MI = SU->getInstr(); in scheduleMI()
1405 if (TII->getMemOpBaseRegImmOfs(*SU->getInstr(), BaseReg, Offset, TRI)) in clusterNeighboringMemOps()
1421 if (TII->shouldClusterMemOps(*SUa->getInstr(), *SUb->getInstr(), in clusterNeighboringMemOps()
1454 if ((IsLoad && !SU->getInstr()->mayLoad()) || in apply()
1455 (!IsLoad && !SU->getInstr()->mayStore())) in apply()
[all …]
DSlotIndexes.cpp179 MachineInstr *SlotMI = ListI->getInstr(); in repairIndexesInRange()
217 if (itr->getInstr()) { in dump()
218 dbgs() << *itr->getInstr(); in dump()
DCriticalAntiDepBreaker.cpp442 MISUnitMap[SU->getInstr()] = SU; in BreakAntiDependencies()
463 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr(); in BreakAntiDependencies()
574 CriticalPathMI = CriticalPathSU->getInstr(); in BreakAntiDependencies()
/external/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp38 MachineInstr *MI = SU->getInstr(); in getHazardType()
83 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMHazardRecognizer.cpp38 MachineInstr *MI = SU->getInstr(); in getHazardType()
84 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
/external/llvm/include/llvm/CodeGen/
DSlotIndexes.h46 MachineInstr* getInstr() const { return mi; } in getInstr() function
432 return index.isValid() ? index.listEntry()->getInstr() : nullptr;
441 if (I->getInstr())
627 assert(miEntry->getInstr() == &MI && "Instruction indexes broken.");
642 assert(miEntry->getInstr() == &MI &&
DScheduleDAG.h389 MachineInstr *getInstr() const {
405 ((SU->getInstr()->mayStore() && this->getInstr()->mayLoad()) ? 1 : 0);
603 if (SU->isInstr()) return &SU->getInstr()->getDesc();
DScheduleDAGInstrs.h248 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr()); in getSchedClass()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyFixIrreducibleControlFlow.cpp207 unsigned Index = MIB.getInstr()->getNumExplicitOperands() - 1; in VisitLoop()
259 MIB.addMBB(MIB.getInstr() in VisitLoop()
260 ->getOperand(MIB.getInstr()->getNumExplicitOperands() - 1) in VisitLoop()
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp436 .getInstr(); in loadImmediate()
440 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr(); in loadImmediate()
448 .getInstr(); in loadImmediate()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DSlotIndexes.h45 MachineInstr* getInstr() const { return mi; } in getInstr() function
502 return index.isValid() ? index.entry().getInstr() : 0;
692 assert(miEntry->getInstr() == mi && "Instruction indexes broken.");
707 assert(miEntry->getInstr() == mi &&
DScheduleDAG.h345 MachineInstr *getInstr() const {
513 if (SU->isInstr()) return &SU->getInstr()->getDesc();
/external/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.cpp331 MachineInstr *MI = SU->getInstr(); in getHazardType()
389 MachineInstr *MI = SU->getInstr(); in EmitInstruction()

12