| /external/llvm/lib/CodeGen/ |
| D | DetectDeadLanes.cpp | 245 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
249 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
269 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
319 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
325 unsigned SubIdx = MI.getOperand(3).getImm(); in transferDefinedLanes() local
337 unsigned SubIdx = MI.getOperand(2).getImm(); in transferDefinedLanes() local
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| D | ExpandPostRAPseudos.cpp | 90 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
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| D | MachineCopyPropagation.cpp | 139 unsigned SubIdx = TRI->getSubRegIndex(PreviousSrc, Src); in isNopCopy() local
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| D | RegisterCoalescer.cpp | 1244 unsigned SubIdx) { in updateRegDefsUses()
1708 const unsigned SubIdx; member in __anon48aa05c90211::JoinVals
1863 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals()
2296 bool JoinVals::usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx, in usesLanes()
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| D | TargetRegisterInfo.cpp | 46 unsigned SubIdx) { in PrintReg()
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| D | MachineInstr.cpp | 77 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, in substVirtReg()
1251 if (unsigned SubIdx = MO.getSubReg()) { in getRegClassConstraintEffect() local
1490 unsigned SubIdx, in substituteRegister()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | Thumb2RegisterInfo.cpp | 38 unsigned DestReg, unsigned SubIdx, in emitLoadConstPool()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegisterCoalescer.h | 42 unsigned SubIdx; variable
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| D | ExpandPostRAPseudos.cpp | 110 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
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| D | TwoAddressInstructionPass.cpp | 1257 unsigned SubIdx = mi->getOperand(3).getImm(); in runOnMachineFunction() local
1290 unsigned DstReg, unsigned SubIdx, in UpdateRegSequenceSrcs()
1455 unsigned SubIdx = MI->getOperand(i+1).getImm(); in EliminateRegSequences() local
1518 unsigned SubIdx = MI->getOperand(i+1).getImm(); in EliminateRegSequences() local
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| D | LiveDebugVariables.cpp | 701 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx, in renameRegister()
717 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { in renameRegister()
733 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { in renameRegister()
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| D | PeepholeOptimizer.cpp | 134 unsigned SrcReg, DstReg, SubIdx; in OptimizeExtInstr() local
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| D | TargetInstrInfoImpl.cpp | 204 unsigned SubIdx, in reMaterialize()
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| D | VirtRegRewriter.cpp | 706 unsigned SubIdx, const TargetRegisterInfo *TRI) { in findSuperReg()
914 unsigned SubIdx = 0; in GetRegForReload() local
1975 unsigned SubIdx = MI.getOperand(i).getSubReg(); in ProcessUses() local
2546 unsigned SubIdx = MO.getSubReg(); in RewriteMBB() local
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | CodeGenRegisters.h | 153 CodeGenRegisterClass *getSubClassWithSubReg(Record *SubIdx) const { in getSubClassWithSubReg()
157 void setSubClassWithSubReg(Record *SubIdx, CodeGenRegisterClass *SubRC) { in setSubClassWithSubReg()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIMachineFunctionInfo.cpp | 187 unsigned SubIdx) { in getSpilledReg()
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| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
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| /external/llvm/lib/Target/ARM/ |
| D | ThumbRegisterInfo.cpp | 65 unsigned SubIdx, int Val, in emitThumb1LoadConstPool()
85 unsigned SubIdx, int Val, in emitThumb2LoadConstPool()
105 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 400 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg()
451 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
489 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
577 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); in EmitRegSequence() local
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 324 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
382 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
703 unsigned SubIdx; variable
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 444 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg()
493 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
534 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
626 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); in EmitRegSequence() local
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| /external/capstone/ |
| D | MCRegisterInfo.c | 86 unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRe… in MCRegisterInfo_getMatchingSuperReg()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 349 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg()
353 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg()
364 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass()
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| D | CodeGenRegisters.cpp | 469 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs() local
898 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, in getSuperRegClasses()
1565 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
1927 for (const auto &SubIdx : SubRegIndices) { in inferSubClassWithSubReg() local
1959 for (auto &SubIdx : SubRegIndices) { in inferMatchingSuperRegClass() local
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 370 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
380 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask()
499 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
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