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Searched refs:StoreToOffset (Results 1 – 18 of 18) sorted by relevance

/art/compiler/utils/
Dassembler_thumb_test.cc335 __ StoreToOffset(kStoreWord, R2, R4, 12); in TEST_F() local
336 __ StoreToOffset(kStoreWord, R2, R4, 0xfff); in TEST_F() local
337 __ StoreToOffset(kStoreWord, R2, R4, 0x1000); in TEST_F() local
338 __ StoreToOffset(kStoreWord, R2, R4, 0x1000a4); in TEST_F() local
339 __ StoreToOffset(kStoreWord, R2, R4, 0x101000); in TEST_F() local
340 __ StoreToOffset(kStoreWord, R4, R4, 0x101000); in TEST_F() local
341 __ StoreToOffset(kStoreHalfword, R2, R4, 12); in TEST_F() local
342 __ StoreToOffset(kStoreHalfword, R2, R4, 0xfff); in TEST_F() local
343 __ StoreToOffset(kStoreHalfword, R2, R4, 0x1000); in TEST_F() local
344 __ StoreToOffset(kStoreHalfword, R2, R4, 0x1000a4); in TEST_F() local
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/art/compiler/utils/mips/
Dassembler_mips_test.cc1572 TEST_F(AssemblerMIPSTest, StoreToOffset) { in TEST_F() argument
1573 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, -0x8000); in TEST_F() local
1574 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0); in TEST_F() local
1575 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0x7FF8); in TEST_F() local
1576 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0x7FFB); in TEST_F() local
1577 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0x7FFC); in TEST_F() local
1578 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, +0x7FFF); in TEST_F() local
1579 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, -0xFFF0); in TEST_F() local
1580 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, -0x8008); in TEST_F() local
1581 __ StoreToOffset(mips::kStoreByte, mips::A3, mips::A1, -0x8001); in TEST_F() local
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Dassembler_mips.cc4733 void MipsAssembler::StoreToOffset(StoreOperandType type, in StoreToOffset() function in art::mips::MipsAssembler
4737 StoreToOffset<>(type, reg, base, offset); in StoreToOffset()
4770 StoreToOffset(kStoreWord, RA, SP, stack_offset); in BuildFrame()
4775 StoreToOffset(kStoreWord, reg, SP, stack_offset); in BuildFrame()
4780 StoreToOffset(kStoreWord, method_reg.AsMips().AsCoreRegister(), SP, 0); in BuildFrame()
4790 StoreToOffset(kStoreWord, reg.AsCoreRegister(), SP, offset); in BuildFrame()
4866 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); in Store()
4869 StoreToOffset(kStoreWord, src.AsRegisterPairLow(), SP, dest.Int32Value()); in Store()
4870 StoreToOffset(kStoreWord, src.AsRegisterPairHigh(), in Store()
4888 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); in StoreRef()
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Dassembler_mips.h1006 void StoreToOffset(StoreOperandType type,
1096 void StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset);
/art/compiler/utils/arm/
Djni_macro_assembler_arm_vixl.cc96 asm_.StoreToOffset(kStoreWord, r0, sp, 0); in BuildFrame()
107 asm_.StoreToOffset(kStoreWord, reg.AsVIXLRegister(), sp, offset); in BuildFrame()
212 asm_.StoreToOffset(kStoreWord, src.AsVIXLRegister(), sp, dest.Int32Value()); in Store()
215 asm_.StoreToOffset(kStoreWord, src.AsVIXLRegisterPairLow(), sp, dest.Int32Value()); in Store()
216 asm_.StoreToOffset(kStoreWord, src.AsVIXLRegisterPairHigh(), sp, dest.Int32Value() + 4); in Store()
232 asm_.StoreToOffset(kStoreWord, src.AsVIXLRegister(), sp, dest.Int32Value()); in StoreRef()
240 asm_.StoreToOffset(kStoreWord, src.AsVIXLRegister(), sp, dest.Int32Value()); in StoreRawPtr()
249 asm_.StoreToOffset(kStoreWord, src.AsVIXLRegister(), sp, dest.Int32Value()); in StoreSpanning()
253 asm_.StoreToOffset(kStoreWord, scratch.AsVIXLRegister(), sp, dest.Int32Value() + 4); in StoreSpanning()
263 asm_.StoreToOffset(kStoreWord, scratch.AsVIXLRegister(), sp, dest.Int32Value()); in CopyRef()
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Dassembler_arm_vixl.h202 void StoreToOffset(StoreOperandType type,
Dassembler_arm_vixl.cc247 void ArmVIXLAssembler::StoreToOffset(StoreOperandType type, in StoreToOffset() function in art::arm::ArmVIXLAssembler
/art/compiler/utils/arm64/
Djni_macro_assembler_arm64.cc55 StoreToOffset(TR, SP, offset.Int32Value()); in GetCurrentThread()
113 void Arm64JNIMacroAssembler::StoreToOffset(XRegister source, XRegister base, int32_t offset) { in StoreToOffset() function in art::arm64::Arm64JNIMacroAssembler
135 StoreToOffset(src.AsXRegister(), SP, offs.Int32Value()); in Store()
154 StoreToOffset(src.AsXRegister(), SP, offs.Int32Value()); in StoreRawPtr()
173 StoreToOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value()); in StoreStackOffsetToThread()
189 StoreToOffset(source.AsXRegister(), SP, dest_off.Int32Value()); in StoreSpanning()
191 StoreToOffset(scratch.AsXRegister(), SP, dest_off.Int32Value() + 8); in StoreSpanning()
366 StoreToOffset(scratch.AsXRegister(), SP, fr_offs.Int32Value()); in CopyRawPtrFromThread()
375 StoreToOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value()); in CopyRawPtrToThread()
399 StoreToOffset(scratch.AsXRegister(), SP, dest.Int32Value()); in Copy()
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Djni_macro_assembler_arm64.h210 void StoreToOffset(XRegister source, XRegister base, int32_t offset);
/art/compiler/utils/mips64/
Dassembler_mips64_test.cc2071 TEST_F(AssemblerMIPS64Test, StoreToOffset) { in TEST_F() argument
2072 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A0, 0); in TEST_F() local
2073 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 0); in TEST_F() local
2074 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 1); in TEST_F() local
2075 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 256); in TEST_F() local
2076 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 1000); in TEST_F() local
2077 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 0x7FFF); in TEST_F() local
2078 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 0x8000); in TEST_F() local
2079 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 0x8001); in TEST_F() local
2080 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 0x10000); in TEST_F() local
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Dassembler_mips64.cc3570 void Mips64Assembler::StoreToOffset(StoreOperandType type, in StoreToOffset() function in art::mips64::Mips64Assembler
3574 StoreToOffset<>(type, reg, base, offset); in StoreToOffset()
3602 StoreToOffset(kStoreDoubleword, RA, SP, stack_offset); in BuildFrame()
3607 StoreToOffset(kStoreDoubleword, reg, SP, stack_offset); in BuildFrame()
3612 StoreToOffset(kStoreDoubleword, method_reg.AsMips64().AsGpuRegister(), SP, 0); in BuildFrame()
3628 StoreToOffset((size == 4) ? kStoreWord : kStoreDoubleword, in BuildFrame()
3686 StoreToOffset(kStoreDoubleword, src.AsGpuRegister(), SP, dest.Int32Value()); in Store()
3688 StoreToOffset(kStoreWord, src.AsGpuRegister(), SP, dest.Int32Value()); in Store()
3707 StoreToOffset(kStoreWord, src.AsGpuRegister(), SP, dest.Int32Value()); in StoreRef()
3713 StoreToOffset(kStoreDoubleword, src.AsGpuRegister(), SP, dest.Int32Value()); in StoreRawPtr()
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Dassembler_mips64.h1216 void StoreToOffset(StoreOperandType type,
1306 void StoreToOffset(StoreOperandType type, GpuRegister reg, GpuRegister base, int32_t offset);
/art/compiler/optimizing/
Dcode_generator_arm_vixl.cc2552 GetAssembler()->StoreToOffset(kStoreWord, kMethodRegister, sp, 0); in GenerateFrameEntry()
2560 GetAssembler()->StoreToOffset(kStoreWord, temp, sp, GetStackOffsetOfShouldDeoptimizeFlag()); in GenerateFrameEntry()
2740 GetAssembler()->StoreToOffset(kStoreWord, in Move32()
2751 GetAssembler()->StoreToOffset(kStoreWord, temp, sp, destination.GetStackIndex()); in Move32()
5471 GetAssembler()->StoreToOffset(operand_type, RegisterFrom(value), base, offset); in HandleFieldSet()
5484 GetAssembler()->StoreToOffset(kStoreWord, temp, base, offset); in HandleFieldSet()
5486 GetAssembler()->StoreToOffset(kStoreWord, RegisterFrom(value), base, offset); in HandleFieldSet()
5501 GetAssembler()->StoreToOffset(kStoreWordPair, LowRegisterFrom(value), base, offset); in HandleFieldSet()
6344 GetAssembler()->StoreToOffset(store_type, RegisterFrom(value_loc), array, full_offset); in VisitArraySet()
6377 GetAssembler()->StoreToOffset(kStoreWord, value, array, offset); in VisitArraySet()
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Dcode_generator_mips64.cc1059 __ StoreToOffset(store_type, in Exchange() local
1063 __ StoreToOffset(store_type, TMP, SP, index1 + stack_offset); in Exchange() local
1121 __ StoreToOffset(kStoreDoubleword, reg, SP, ofs); in GenerateFrameEntry() local
1139 __ StoreToOffset(kStoreDoubleword, kMethodRegisterArgument, SP, kCurrentMethodStackOffset); in GenerateFrameEntry() local
1144 __ StoreToOffset(kStoreWord, ZERO, SP, GetStackOffsetOfShouldDeoptimizeFlag()); in GenerateFrameEntry() local
1333 __ StoreToOffset(store_type, in MoveLocation() local
1362 __ StoreToOffset(store_type, gpr, SP, destination.GetStackIndex()); in MoveLocation() local
1369 __ StoreToOffset(kStoreWord, TMP, SP, destination.GetStackIndex()); in MoveLocation() local
1372 __ StoreToOffset(kStoreDoubleword, TMP, SP, destination.GetStackIndex()); in MoveLocation() local
1440 __ StoreToOffset(store_type, reg_loc.AsRegister<GpuRegister>(), SP, mem_loc.GetStackIndex()); in SwapLocations() local
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Dcode_generator_mips.cc1173 __ StoreToOffset(kStoreWord, TMP, SP, offset); in EmitSwap() local
1185 __ StoreToOffset(kStoreWord, TMP, SP, offset_l); in EmitSwap() local
1188 __ StoreToOffset(kStoreWord, TMP, SP, offset_h); in EmitSwap() local
1239 __ StoreToOffset(kStoreWord, in Exchange() local
1243 __ StoreToOffset(kStoreWord, TMP, SP, index1 + stack_offset); in Exchange() local
1324 __ StoreToOffset(kStoreWord, reg, SP, ofs); in GenerateFrameEntry() local
1341 __ StoreToOffset(kStoreWord, kMethodRegisterArgument, SP, kCurrentMethodStackOffset); in GenerateFrameEntry() local
1346 __ StoreToOffset(kStoreWord, ZERO, SP, GetStackOffsetOfShouldDeoptimizeFlag()); in GenerateFrameEntry() local
1488 __ StoreToOffset(kStoreDoubleword, source.AsRegisterPairLow<Register>(), SP, dst_offset); in MoveLocation() local
1495 __ StoreToOffset(kStoreWord, TMP, SP, dst_offset); in MoveLocation() local
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Dintrinsics_mips64.cc2023 __ StoreToOffset(kStoreHalfword, TMP, dstPtr, 0); in VisitStringGetCharsNoCheck() local
2597 __ StoreToOffset(kStoreWord, in, out, info.value_offset); in VisitIntegerValueOf() local
2620 __ StoreToOffset(kStoreWord, ZERO, TR, offset); in VisitThreadInterrupted() local
Dintrinsics_mips.cc2716 __ StoreToOffset(kStoreHalfword, TMP, dstPtr, 0); in VisitStringGetCharsNoCheck() local
3214 __ StoreToOffset(kStoreWord, in, out, info.value_offset); in VisitIntegerValueOf() local
3237 __ StoreToOffset(kStoreWord, ZERO, TR, offset); in VisitThreadInterrupted() local
Dintrinsics_arm_vixl.cc3308 assembler->StoreToOffset(kStoreWord, temp, out, info.value_offset); in VisitIntegerValueOf()
3333 assembler->StoreToOffset(kStoreWord, in, out, info.value_offset); in VisitIntegerValueOf()
3359 assembler->StoreToOffset(kStoreWord, temp, tr, offset); in VisitThreadInterrupted()