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/external/swiftshader/third_party/subzero/pydir/
Dgen_arm32_reg_tables.py60 class Reg(object): class
82 Reg( 'r0', 0, IsScratch=1, CCArg=1, IsGPR = 1, IsInt=1, Aliases= 'r0, r0r1'),
83 Reg( 'r1', 1, IsScratch=1, CCArg=2, IsGPR = 1, IsInt=1, Aliases= 'r1, r0r1'),
84 Reg( 'r2', 2, IsScratch=1, CCArg=3, IsGPR = 1, IsInt=1, Aliases= 'r2, r2r3'),
85 Reg( 'r3', 3, IsScratch=1, CCArg=4, IsGPR = 1, IsInt=1, Aliases= 'r3, r2r3'),
86 Reg( 'r4', 4, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r4, r4r5'),
87 Reg( 'r5', 5, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r5, r4r5'),
88 Reg( 'r6', 6, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r6, r6r7'),
89 Reg( 'r7', 7, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r7, r6r7'),
90 Reg( 'r8', 8, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r8, r8r9'),
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/external/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp39 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() argument
41 VRegInfo[Reg].first = RC; in setRegClass()
44 void MachineRegisterInfo::setRegBank(unsigned Reg, in setRegBank() argument
46 VRegInfo[Reg].first = &RegBank; in setRegBank()
50 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() argument
53 const TargetRegisterClass *OldRC = getRegClass(Reg); in constrainRegClass()
62 setRegClass(Reg, NewRC); in constrainRegClass()
67 MachineRegisterInfo::recomputeRegClass(unsigned Reg) { in recomputeRegClass() argument
69 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
78 for (MachineOperand &MO : reg_nodbg_operands(Reg)) { in recomputeRegClass()
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DAggressiveAntiDepBreaker.cpp60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
61 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
74 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
75 Regs.push_back(Reg); in GetGroupRegs()
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) in LeaveGroup() argument
102 GroupNodeIndices[Reg] = idx; in LeaveGroup()
106 bool AggressiveAntiDepState::IsLive(unsigned Reg) in IsLive() argument
110 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
154 unsigned Reg = *AI; in StartBlock() local
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DLiveVariables.cpp182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr &MI) { in HandleVirtRegDef() argument
183 VarInfo &VRInfo = getVarInfo(Reg); in HandleVirtRegDef()
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, in FindLastPartialDef() argument
197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastPartialDef()
219 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr &MI) { in HandlePhysRegUse() argument
232 MachineInstr *LastDef = PhysRegDef[Reg]; in HandlePhysRegUse()
234 if (!LastDef && !PhysRegUse[Reg]) { in HandlePhysRegUse()
244 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs); in HandlePhysRegUse()
247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
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DCriticalAntiDepBreaker.cpp62 unsigned Reg = *AI; in StartBlock() local
63 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
64 KillIndices[Reg] = BBSize; in StartBlock()
65 DefIndices[Reg] = ~0u; in StartBlock()
77 unsigned Reg = *AI; in StartBlock() local
78 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
79 KillIndices[Reg] = BBSize; in StartBlock()
80 DefIndices[Reg] = ~0u; in StartBlock()
103 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local
104 if (KillIndices[Reg] != ~0u) { in Observe()
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DMachineInstrBundle.cpp146 unsigned Reg = MO.getReg(); in finalizeBundle() local
147 if (!Reg) in finalizeBundle()
149 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); in finalizeBundle()
150 if (LocalDefSet.count(Reg)) { in finalizeBundle()
154 KilledDefSet.insert(Reg); in finalizeBundle()
156 if (ExternUseSet.insert(Reg).second) { in finalizeBundle()
157 ExternUses.push_back(Reg); in finalizeBundle()
159 UndefUseSet.insert(Reg); in finalizeBundle()
163 KilledUseSet.insert(Reg); in finalizeBundle()
169 unsigned Reg = MO.getReg(); in finalizeBundle() local
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DLivePhysRegs.cpp51 unsigned Reg = O->getReg(); in stepBackward() local
52 if (Reg == 0) in stepBackward()
54 removeReg(Reg); in stepBackward()
63 unsigned Reg = O->getReg(); in stepBackward() local
64 if (Reg == 0) in stepBackward()
66 addReg(Reg); in stepBackward()
79 unsigned Reg = O->getReg(); in stepForward() local
80 if (Reg == 0) in stepForward()
85 Clobbers.push_back(std::make_pair(Reg, &*O)); in stepForward()
90 removeReg(Reg); in stepForward()
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DMachineVerifier.cpp91 void addRegWithSubRegs(RegVector &RV, unsigned Reg) { in addRegWithSubRegs()
92 RV.push_back(Reg); in addRegWithSubRegs()
93 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in addRegWithSubRegs()
94 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in addRegWithSubRegs()
129 bool addPassed(unsigned Reg) { in addPassed()
130 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in addPassed()
132 if (regsKilled.count(Reg) || regsLiveOut.count(Reg)) in addPassed()
134 return vregsPassed.insert(Reg).second; in addPassed()
148 bool addRequired(unsigned Reg) { in addRequired()
149 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in addRequired()
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DRegisterScavenging.cpp34 void RegScavenger::setRegUsed(unsigned Reg, LaneBitmask LaneMask) { in setRegUsed() argument
35 for (MCRegUnitMaskIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) { in setRegUsed()
45 I->Reg = 0; in initRegState()
92 void RegScavenger::addRegUnits(BitVector &BV, unsigned Reg) { in addRegUnits() argument
93 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in addRegUnits()
124 unsigned Reg = MO.getReg(); in determineKillsAndDefs() local
125 if (!TargetRegisterInfo::isPhysicalRegister(Reg) || isReserved(Reg)) in determineKillsAndDefs()
133 addRegUnits(KillRegUnits, Reg); in determineKillsAndDefs()
137 addRegUnits(KillRegUnits, Reg); in determineKillsAndDefs()
139 addRegUnits(DefRegUnits, Reg); in determineKillsAndDefs()
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/external/llvm/test/MC/Lanai/
Dmemory.s10 ! CHECK-NEXT: <MCOperand Reg:13>
11 ! CHECK-NEXT: <MCOperand Reg:14>
18 ! CHECK-NEXT: <MCOperand Reg:13>
19 ! CHECK-NEXT: <MCOperand Reg:13>
26 ! CHECK-NEXT: <MCOperand Reg:13>
27 ! CHECK-NEXT: <MCOperand Reg:14>
34 ! CHECK-NEXT: <MCOperand Reg:13>
35 ! CHECK-NEXT: <MCOperand Reg:14>
42 ! CHECK-NEXT: <MCOperand Reg:13>
43 ! CHECK-NEXT: <MCOperand Reg:14>
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/external/swiftshader/third_party/LLVM/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
62 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
75 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
76 Regs.push_back(Reg); in GetGroupRegs()
96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) in LeaveGroup() argument
103 GroupNodeIndices[Reg] = idx; in LeaveGroup()
107 bool AggressiveAntiDepState::IsLive(unsigned Reg) in IsLive() argument
111 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
161 unsigned Reg = *Alias; ++Alias) { in StartBlock()
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DCriticalAntiDepBreaker.cpp64 unsigned Reg = *I; in StartBlock() local
65 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
66 KillIndices[Reg] = BB->size(); in StartBlock()
67 DefIndices[Reg] = ~0u; in StartBlock()
70 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { in StartBlock()
86 unsigned Reg = *I; in StartBlock() local
87 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
88 KillIndices[Reg] = BB->size(); in StartBlock()
89 DefIndices[Reg] = ~0u; in StartBlock()
92 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { in StartBlock()
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DMachineRegisterInfo.cpp46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() argument
47 VRegInfo[Reg].first = RC; in setRegClass()
51 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() argument
54 const TargetRegisterClass *OldRC = getRegClass(Reg); in constrainRegClass()
62 setRegClass(Reg, NewRC); in constrainRegClass()
67 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { in recomputeRegClass() argument
69 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
77 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; in recomputeRegClass()
89 setRegClass(Reg, NewRC); in recomputeRegClass()
103 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); in createVirtualRegister() local
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DLiveVariables.cpp178 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { in HandleVirtRegDef() argument
179 VarInfo &VRInfo = getVarInfo(Reg); in HandleVirtRegDef()
188 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, in FindLastPartialDef() argument
193 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in FindLastPartialDef()
215 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
228 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { in HandlePhysRegUse() argument
229 MachineInstr *LastDef = PhysRegDef[Reg]; in HandlePhysRegUse()
231 if (!LastDef && !PhysRegUse[Reg]) { in HandlePhysRegUse()
241 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs); in HandlePhysRegUse()
244 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
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DProcessImplicitDefs.cpp49 unsigned Reg, unsigned OpIdx, in CanTurnIntoImplicitDef() argument
62 static bool isUndefCopy(MachineInstr *MI, unsigned Reg, in isUndefCopy() argument
67 if (MO1.getReg() != Reg) in isUndefCopy()
110 unsigned Reg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
111 ImpDefRegs.insert(Reg); in runOnMachineFunction()
112 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { in runOnMachineFunction()
113 for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS) in runOnMachineFunction()
128 unsigned Reg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
134 if (TargetRegisterInfo::isVirtualRegister(Reg) && MRI->def_empty(Reg)) in runOnMachineFunction()
135 ImpDefRegs.insert(Reg); in runOnMachineFunction()
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DRegisterScavenging.cpp37 void RegScavenger::setUsed(unsigned Reg) { in setUsed() argument
38 RegsAvailable.reset(Reg); in setUsed()
40 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in setUsed()
45 bool RegScavenger::isAliasUsed(unsigned Reg) const { in isAliasUsed()
46 if (isUsed(Reg)) in isAliasUsed()
48 for (const unsigned *R = TRI->getAliasSet(Reg); *R; ++R) in isAliasUsed()
111 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) { in addRegWithSubRegs() argument
112 BV.set(Reg); in addRegWithSubRegs()
113 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++) in addRegWithSubRegs()
117 void RegScavenger::addRegWithAliases(BitVector &BV, unsigned Reg) { in addRegWithAliases() argument
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/external/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h44 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
94 return MO->Contents.Reg.Next; in getNextOperandForReg()
220 void verifyUseList(unsigned Reg) const;
252 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const { in reg_operands() argument
253 return make_range(reg_begin(Reg), reg_end()); in reg_operands()
268 reg_instructions(unsigned Reg) const { in reg_instructions() argument
269 return make_range(reg_instr_begin(Reg), reg_instr_end()); in reg_instructions()
283 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const { in reg_bundles() argument
284 return make_range(reg_bundle_begin(Reg), reg_bundle_end()); in reg_bundles()
303 reg_nodbg_operands(unsigned Reg) const { in reg_nodbg_operands() argument
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DLiveIntervalAnalysis.h109 LiveInterval &getInterval(unsigned Reg) { in getInterval() argument
110 if (hasInterval(Reg)) in getInterval()
111 return *VirtRegIntervals[Reg]; in getInterval()
113 return createAndComputeVirtRegInterval(Reg); in getInterval()
116 const LiveInterval &getInterval(unsigned Reg) const { in getInterval() argument
117 return const_cast<LiveIntervals*>(this)->getInterval(Reg); in getInterval()
120 bool hasInterval(unsigned Reg) const { in hasInterval() argument
121 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg]; in hasInterval()
125 LiveInterval &createEmptyInterval(unsigned Reg) { in createEmptyInterval() argument
126 assert(!hasInterval(Reg) && "Interval already exists!"); in createEmptyInterval()
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/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetRegisterInfo.h81 bool contains(unsigned Reg) const { in contains() argument
82 return MC->contains(Reg); in contains()
253 static bool isStackSlot(unsigned Reg) { in isStackSlot() argument
254 return int(Reg) >= (1 << 30); in isStackSlot()
259 static int stackSlot2Index(unsigned Reg) { in stackSlot2Index() argument
260 assert(isStackSlot(Reg) && "Not a stack slot"); in stackSlot2Index()
261 return int(Reg - (1u << 30)); in stackSlot2Index()
273 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument
274 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); in isPhysicalRegister()
275 return int(Reg) > 0; in isPhysicalRegister()
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineRegisterInfo.h193 MachineInstr *getVRegDef(unsigned Reg) const;
199 void clearKillFlags(unsigned Reg) const;
211 const TargetRegisterClass *getRegClass(unsigned Reg) const { in getRegClass() argument
212 return VRegInfo[Reg].first; in getRegClass()
217 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
226 const TargetRegisterClass *constrainRegClass(unsigned Reg,
238 bool recomputeRegClass(unsigned Reg, const TargetMachine&);
251 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { in setRegAllocationHint() argument
252 RegAllocHints[Reg].first = Type; in setRegAllocationHint()
253 RegAllocHints[Reg].second = PrefReg; in setRegAllocationHint()
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/external/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp66 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
90 unsigned Reg = MI->getOperand(1).getReg(); in getAccDefMI() local
91 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in getAccDefMI()
95 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
100 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
101 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in getAccDefMI()
102 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
106 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
107 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in getAccDefMI()
108 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
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/external/capstone/arch/Mips/
DMipsDisassembler.c770 unsigned Reg; in DecodeGPR64RegisterClass() local
775 Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo); in DecodeGPR64RegisterClass()
776 MCOperand_CreateReg0(Inst, Reg); in DecodeGPR64RegisterClass()
783 unsigned Reg; in DecodeGPR32RegisterClass() local
788 Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo); in DecodeGPR32RegisterClass()
789 MCOperand_CreateReg0(Inst, Reg); in DecodeGPR32RegisterClass()
811 unsigned Reg; in DecodeFGR64RegisterClass() local
816 Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo); in DecodeFGR64RegisterClass()
817 MCOperand_CreateReg0(Inst, Reg); in DecodeFGR64RegisterClass()
824 unsigned Reg; in DecodeFGR32RegisterClass() local
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/external/llvm/lib/Target/SystemZ/AsmParser/
DSystemZAsmParser.cpp113 RegOp Reg; member
148 Op->Reg.Kind = Kind; in createReg()
149 Op->Reg.Num = Num; in createReg()
200 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
204 return Reg.Num; in getReg()
365 bool parseRegister(Register &Reg);
367 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
498 bool SystemZAsmParser::parseRegister(Register &Reg) { in parseRegister() argument
499 Reg.StartLoc = Parser.getTok().getLoc(); in parseRegister()
508 return Error(Reg.StartLoc, "invalid register"); in parseRegister()
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/
DPTXMachineFunctionInfo.h82 void addRetReg(unsigned Reg) { in addRetReg() argument
83 if (!RegRets.count(Reg)) { in addRetReg()
84 RegRets.insert(Reg); in addRetReg()
88 RegNames[Reg] = name; in addRetReg()
93 void addArgReg(unsigned Reg) { in addArgReg() argument
94 RegArgs.insert(Reg); in addArgReg()
98 RegNames[Reg] = name; in addArgReg()
103 void addVirtualRegister(const TargetRegisterClass *TRC, unsigned Reg) { in addVirtualRegister() argument
107 if (!RegRets.count(Reg) && !RegArgs.count(Reg)) { in addVirtualRegister()
108 UsedRegs[TRC].push_back(Reg); in addVirtualRegister()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DMLxExpansionPass.cpp63 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
87 unsigned Reg = MI->getOperand(1).getReg(); in getAccDefMI() local
88 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in getAccDefMI()
92 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
97 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
98 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in getAccDefMI()
99 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
103 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
104 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in getAccDefMI()
105 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
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