Home
last modified time | relevance | path

Searched refs:sll (Results 1 – 25 of 264) sorted by relevance

1234567891011

/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dvector-icmp.ll39 ; MIPS32: sll [[T4]],[[T4]],0x1f
42 ; MIPS32: sll [[T5]],[[T5]],0x1f
45 ; MIPS32: sll [[T6]],[[T6]],0x1f
48 ; MIPS32: sll [[T7]],[[T7]],0x1f
287 ; MIPS32: sll [[T4]],[[T4]],0x1f
288 ; MIPS32: sll [[T0]],[[T0]],0x1f
293 ; MIPS32: sll [[T5]],[[T5]],0x1f
294 ; MIPS32: sll [[T1]],[[T1]],0x1f
299 ; MIPS32: sll [[T6]],[[T6]],0x1f
300 ; MIPS32: sll [[T2]],[[T2]],0x1f
[all …]
Dvector-cast.ll39 ; MIPS32: sll t2,t2,0x1f
43 ; MIPS32: sll v0,v0,0x8
49 ; MIPS32: sll v0,v0,0x1f
52 ; MIPS32: sll v0,v0,0x8
61 ; MIPS32: sll t2,t2,0x1f
64 ; MIPS32: sll t2,t2,0x10
71 ; MIPS32: sll a0,a0,0x1f
73 ; MIPS32: sll a0,a0,0x18
74 ; MIPS32: sll t2,t2,0x8
80 ; MIPS32: sll v0,v0,0x1f
[all …]
Dvector-select.ll60 ; MIPS32: sll [[T14]],[[T14]],0x8
74 ; MIPS32: sll [[T2]],[[T2]],0x8
91 ; MIPS32: sll [[T1]],[[T1]],0x10
101 ; MIPS32: sll [[T10]],[[T10]],0x18
102 ; MIPS32: sll [[T1]],[[T1]],0x8
115 ; MIPS32: sll [[T15]],[[T15]],0x8
129 ; MIPS32: sll [[T15]],[[T15]],0x8
146 ; MIPS32: sll [[T14]],[[T14]],0x10
156 ; MIPS32: sll [[T11]],[[T11]],0x18
157 ; MIPS32: sll [[T14]],[[T14]],0x8
[all …]
Dicmp.ll119 ; MIPS32: sll {{.*}}, {{.*}}, 24
120 ; MIPS32: sll {{.*}}, {{.*}}, 24
133 ; MIPS32: sll {{.*}}, {{.*}}, 24
134 ; MIPS32: sll {{.*}}, {{.*}}, 24
146 ; MIPS32: sll {{.*}}, {{.*}}, 24
147 ; MIPS32: sll {{.*}}, {{.*}}, 24
159 ; MIPS32: sll {{.*}}, {{.*}}, 16
160 ; MIPS32: sll {{.*}}, {{.*}}, 16
172 ; MIPS32: sll {{.*}}, {{.*}}, 16
173 ; MIPS32: sll {{.*}}, {{.*}}, 16
/external/clang/test/CodeGen/
DAtomics.c11 signed long long sll; variable
22 (void) __sync_fetch_and_add (&sll, 1); // CHECK: atomicrmw add i64 in test_op_ignore()
31 (void) __sync_fetch_and_sub (&sll, 1); // CHECK: atomicrmw sub i64 in test_op_ignore()
40 (void) __sync_fetch_and_or (&sll, 1); // CHECK: atomicrmw or i64 in test_op_ignore()
49 (void) __sync_fetch_and_xor (&sll, 1); // CHECK: atomicrmw xor i64 in test_op_ignore()
58 (void) __sync_fetch_and_nand (&sll, 1); // CHECK: atomicrmw nand i64 in test_op_ignore()
67 (void) __sync_fetch_and_and (&sll, 1); // CHECK: atomicrmw and i64 in test_op_ignore()
80 sll = __sync_fetch_and_add (&sll, 11); // CHECK: atomicrmw add in test_fetch_and_op()
89 sll = __sync_fetch_and_sub (&sll, 11); // CHECK: atomicrmw sub in test_fetch_and_op()
98 sll = __sync_fetch_and_or (&sll, 11); // CHECK: atomicrmw or in test_fetch_and_op()
[all …]
Dcomplex-convert.c11 void foo(signed char sc, unsigned char uc, signed long long sll, in foo() argument
138 csc1 = sll; in foo()
168 cuc1 = sll; in foo()
200 csll1 = sll; in foo()
230 cull1 = sll; in foo()
372 csll1 = sll + csc; in foo()
387 csll1 = sll + cuc; in foo()
402 csll1 = sll + csll; in foo()
415 csll1 = sll + cull; in foo()
520 csll1 = csc + sll; in foo()
[all …]
Dbuiltins-nvptx.c190 __shared__ long long sll; variable
201 __nvvm_atom_add_gen_ll(&sll, ll); in nvvm_atom()
208 __nvvm_atom_sub_gen_ll(&sll, ll); in nvvm_atom()
215 __nvvm_atom_and_gen_ll(&sll, ll); in nvvm_atom()
222 __nvvm_atom_or_gen_ll(&sll, ll); in nvvm_atom()
229 __nvvm_atom_xor_gen_ll(&sll, ll); in nvvm_atom()
236 __nvvm_atom_xchg_gen_ll(&sll, ll); in nvvm_atom()
247 __nvvm_atom_max_gen_ll(&sll, ll); in nvvm_atom()
249 __nvvm_atom_max_gen_ull((unsigned long long *)&sll, ll); in nvvm_atom()
260 __nvvm_atom_min_gen_ll(&sll, ll); in nvvm_atom()
[all …]
DNontemporal.cpp10 signed long long sll; variable
29 __builtin_nontemporal_store(1, &sll); // CHECK: store i64{{.*}}align 8, !nontemporal in test_all_sizes()
42 ull = __builtin_nontemporal_load(&sll); // CHECK: load i64{{.*}}align 8, !nontemporal in test_all_sizes()
43 sll = __builtin_nontemporal_load(&ull); // CHECK: load i64{{.*}}align 8, !nontemporal in test_all_sizes()
/external/llvm/test/CodeGen/Hexagon/
DAtomics.ll4 @sll = common global i64 0, align 8
9 %t01 = atomicrmw add i64* @sll, i64 1 monotonic
11 %t11 = atomicrmw sub i64* @sll, i64 1 monotonic
13 %t21 = atomicrmw or i64* @sll, i64 1 monotonic
15 %t31 = atomicrmw xor i64* @sll, i64 1 monotonic
17 %t41 = atomicrmw and i64* @sll, i64 1 monotonic
19 %t51 = atomicrmw nand i64* @sll, i64 1 monotonic
30 %t01 = atomicrmw add i64* @sll, i64 11 monotonic
31 store i64 %t01, i64* @sll, align 8
34 %t11 = atomicrmw sub i64* @sll, i64 11 monotonic
[all …]
/external/iputils/
Drarpd.c419 struct sockaddr_ll sll; in serve_it() local
420 socklen_t sll_len = sizeof(sll); in serve_it()
426 n = recvfrom(fd, buf, sizeof(buf), MSG_DONTWAIT, (struct sockaddr*)&sll, &sll_len); in serve_it()
434 if (sll.sll_pkttype != PACKET_BROADCAST && in serve_it()
435 sll.sll_pkttype != PACKET_MULTICAST && in serve_it()
436 sll.sll_pkttype != PACKET_HOST) in serve_it()
439 if (ifidx && sll.sll_ifindex != ifidx) in serve_it()
455 for (i=0; i<sll.sll_halen; i++) { in serve_it()
457 sprintf(ptr, ":%02x", sll.sll_addr[i]); in serve_it()
460 sprintf(ptr, "%02x", sll.sll_addr[i]); in serve_it()
[all …]
/external/llvm/test/MC/Mips/
Dmips-expansions.s145 # CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00]
149 # CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00]
155 # CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00]
159 # CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00]
166 # CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00]
171 # CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
177 # CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00]
181 # CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00]
188 # CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00]
193 # CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
[all …]
Dmicromips-shift-instructions.s10 # CHECK-EL: sll $4, $3, 7 # encoding: [0x83,0x00,0x00,0x38]
24 # CHECK-EL: sll $3, $3, 7 # encoding: [0x63,0x00,0x00,0x38]
30 # CHECK-EB: sll $4, $3, 7 # encoding: [0x00,0x83,0x38,0x00]
44 # CHECK-EB: sll $3, $3, 7 # encoding: [0x00,0x63,0x38,0x00]
47 sll $4, $3, 7
55 sll $2, $3, $5
58 sll $2, $3
61 sll $3, 7
Drotations32.s30 # CHECK-32: sll $1, $4, 1 # encoding: [0x00,0x04,0x08,0x40]
35 # CHECK-32: sll $1, $5, 1 # encoding: [0x00,0x05,0x08,0x40]
40 # CHECK-32: sll $1, $4, 2 # encoding: [0x00,0x04,0x08,0x80]
45 # CHECK-32: sll $1, $5, 2 # encoding: [0x00,0x05,0x08,0x80]
70 # CHECK-32: sll $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc0]
75 # CHECK-32: sll $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc0]
80 # CHECK-32: sll $4, $4, 30 # encoding: [0x00,0x04,0x27,0x80]
85 # CHECK-32: sll $4, $5, 30 # encoding: [0x00,0x05,0x27,0x80]
/external/llvm/test/CodeGen/SystemZ/
Dshift-01.ll8 ; CHECK: sll %r2, 1
17 ; CHECK: sll %r2, 31
26 ; CHECK-NOT: sll %r2, 32
35 ; CHECK-NOT: sll %r2, -1{{.*}}
45 ; CHECK: sll %r2, 0(%r3)
54 ; CHECK: sll %r2, 10(%r3)
64 ; CHECK: sll %r2, 10(%r3)
76 ; CHECK: sll %r2, 4095(%r3)
87 ; CHECK: sll %r2, 0(%r3)
98 ; CHECK: sll %r2, 0({{%r[34]}})
[all …]
Datomicrmw-minmax-02.ll18 ; CHECK: sll %r2, 3
32 ; CHECK-SHIFT1: sll %r2, 3
40 ; CHECK-SHIFT2: sll %r3, 16
54 ; CHECK: sll %r2, 3
68 ; CHECK-SHIFT1: sll %r2, 3
76 ; CHECK-SHIFT2: sll %r3, 16
90 ; CHECK: sll %r2, 3
104 ; CHECK-SHIFT1: sll %r2, 3
112 ; CHECK-SHIFT2: sll %r3, 16
126 ; CHECK: sll %r2, 3
[all …]
Datomicrmw-minmax-01.ll18 ; CHECK: sll %r2, 3
32 ; CHECK-SHIFT1: sll %r2, 3
40 ; CHECK-SHIFT2: sll %r3, 24
54 ; CHECK: sll %r2, 3
68 ; CHECK-SHIFT1: sll %r2, 3
76 ; CHECK-SHIFT2: sll %r3, 24
90 ; CHECK: sll %r2, 3
104 ; CHECK-SHIFT1: sll %r2, 3
112 ; CHECK-SHIFT2: sll %r3, 24
126 ; CHECK: sll %r2, 3
[all …]
/external/llvm/test/CodeGen/Mips/
Dmadd-msub.ll34 ; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
35 ; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
38 ; 64-DAG: sll $[[T3:[0-9]+]], $6, 0
41 ; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
42 ; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
44 ; 64R6-DAG: sll $[[T3:[0-9]+]], $6, 0
117 ; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
118 ; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
123 ; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
124 ; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
[all …]
Dunalignedload.ll22 ; MIPS32-EL-DAG: sll $[[T0:[0-9]+]], $[[PART2]], 8
27 ; MIPS32-EB-DAG: sll $[[T0:[0-9]+]], $[[PART1]], 8
29 ; MIPS32-EB-DAG: sll $4, $[[T1]], 16
48 ; MIPS32-EL-DAG: sll $[[T3:[0-9]+]], $[[T1]], 8
50 ; MIPS32-EL-DAG: sll $[[T5:[0-9]+]], $[[T2]], 16
58 ; MIPS32-EB-DAG: sll $[[T3:[0-9]+]], $[[T0]], 8
60 ; MIPS32-EB-DAG: sll $[[T5:[0-9]+]], $[[T4]], 16
61 ; MIPS32-EB-DAG: sll $[[T6:[0-9]+]], $[[T2]], 8
68 ; MIPS32R6-EL-DAG: sll $[[T2:[0-9]+]], $[[T1]], 16
75 ; MIPS32R6-EB-DAG: sll $[[T2:[0-9]+]], $[[T0]], 16
[all …]
Dconst-mult.ll5 ; CHECK: sll $[[R0:[0-9]+]], $4, 2
15 ; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
17 ; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 5
27 ; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
29 ; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 31
Datomic.ll137 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
138 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
162 ; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 24
181 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
183 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
207 ; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 24
226 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
228 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
253 ; NO-SEB-SEH: sll $[[R20:[0-9]+]], $[[R19]], 24
272 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
[all …]
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dmul.ll38 ; M2: sll $[[T0]], $[[T0]], 31
42 ; 32R1-R5: sll $[[T0]], $[[T0]], 31
46 ; 32R6: sll $[[T0]], $[[T0]], 31
51 ; M4: sll $[[T0]], $[[T0]], 31
55 ; 64R1-R5: sll $[[T0]], $[[T0]], 31
59 ; 64R6: sll $[[T0]], $[[T0]], 31
63 ; MM32: sll $[[T0]], $[[T0]], 31
76 ; M2: sll $[[T0]], $[[T0]], 24
80 ; 32R1: sll $[[T0]], $[[T0]], 24
91 ; M4: sll $[[T0]], $[[T0]], 24
[all …]
Dsdiv.ll43 ; FIXME: The sll/sra instructions are redundant since div is signed.
44 ; NOT-R6: sll $[[T1:[0-9]+]], $[[T0]], 31
49 ; FIXME: The sll/sra instructions are redundant since div is signed.
50 ; R6: sll $[[T1:[0-9]+]], $[[T0]], 31
56 ; MMR3: sll $[[T1:[0-9]+]], $[[T0]], 31
61 ; MMR6: sll $[[T1:[0-9]+]], $[[T0]], 31
75 ; FIXME: The sll/sra instructions are redundant since div is signed.
76 ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24
110 ; FIXME: The sll/sra instructions are redundant since div is signed.
111 ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16
/external/valgrind/none/tests/mips64/
Dshift_instructions.stdout.exp-mips6413825 sll $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
13826 sll $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
13827 sll $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
13828 sll $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
13829 sll $t0, $t1, 0x00 :: rt 0x12bd6aa, rs 0x12bd6aa, imm 0x0000
13830 sll $t2, $t3, 0x1f :: rt 0x0, rs 0x12bd6aa, imm 0x001f
13831 sll $a0, $a1, 0x0f :: rt 0xffffffffeb550000, rs 0x12bd6aa, imm 0x000f
13832 sll $s0, $s1, 0x03 :: rt 0x95eb550, rs 0x12bd6aa, imm 0x0003
13833 sll $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
13834 sll $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
[all …]
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dcallabi.ll15 ; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 24
30 ; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 16
58 ; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 24
60 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24
77 ; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 16
79 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 16
110 ; 32R1-DAG: sll $[[T3:[0-9]+]], $[[T0]], 24
112 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24
114 ; 32R1-DAG: sll $[[T5:[0-9]+]], $[[T2]], 24
133 ; 32R1-DAG: sll $[[T3:[0-9]+]], $[[T0]], 16
[all …]
/external/iproute2/misc/
Darpd.c190 struct sockaddr_ll sll = { in send_probe() local
223 memset(sll.sll_addr, 0xFF, sizeof(sll.sll_addr)); in send_probe()
224 memcpy(p, &sll.sll_addr, ah->ar_hln); in send_probe()
230 if (sendto(pset[0].fd, buf, p-buf, 0, (struct sockaddr *)&sll, sizeof(sll)) < 0) in send_probe()
481 struct sockaddr_ll sll; in get_arp_pkt() local
482 socklen_t sll_len = sizeof(sll); in get_arp_pkt()
489 (struct sockaddr *)&sll, &sll_len); in get_arp_pkt()
496 if (ifnum && !handle_if(sll.sll_ifindex)) in get_arp_pkt()
506 a->ar_hln != sll.sll_halen || in get_arp_pkt()
510 key.iface = sll.sll_ifindex; in get_arp_pkt()
[all …]

1234567891011