Home
last modified time | relevance | path

Searched refs:CM_CLKSEL1 (Results 1 – 7 of 7) sorted by relevance

/arch/arm/mach-omap2/
Dclock24xx.c368 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; in omap2_select_table_rate()
369 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1); in omap2_select_table_rate()
403 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); in omap2_get_apll_clkin()
Dcm.h66 #define CM_CLKSEL1 CM_CLKSEL macro
Dclock24xx.h673 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
753 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
793 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
826 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
1183 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1213 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1245 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1285 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1452 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1485 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
[all …]
Dclock34xx.h387 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
472 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
525 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
740 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
767 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
835 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2868 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2892 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2915 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2931 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
[all …]
Dsram34xx.S160 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
Dsram243x.S314 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
Dsram242x.S314 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)