| /arch/arm/boot/compressed/ |
| D | head-sharpsl.S | 35 mrc p15, 0, r4, c0, c0 @ Get Processor ID
53 ldr r6, [r1, #0] @ Load Chip ID
96 .word 0x69052d00 @ PXA255 Processor ID
98 .word 0x69054100 @ PXA270 Processor ID
100 .word 0x57411002 @ w100 Chip ID
102 .word 0x08010000 @ w100 Chip ID Reg Address
146 ldrb r2, [r1, #20] @ NAND Manufacturer ID
147 ldrb r3, [r1, #20] @ NAND Chip ID
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| D | head-l7200.S | 29 mov r7, #MACH_TYPE_L7200 @ Set architecture ID
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| D | head.S | 124 1: mov r7, r1 @ save architecture ID
540 mrc p15, 0, r6, c0, c0 @ get processor ID
577 .word 0x00000000 @ old ARM ID
613 @ Everything from here on will be the new ID system.
639 @ These match on the architecture ID
854 teq r3, r6 @ cache ID register present?
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| /arch/arm/mm/ |
| D | cache-v4.S | 33 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
52 mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache
120 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
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| D | cache-v3.S | 45 mcreq p15, 0, ip, c7, c0, 0 @ flush ID cache
109 mcr p15, 0, r0, c7, c0, 0 @ flush ID cache
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| D | proc-v7.S | 98 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
102 mcr p15, 0, r1, c13, c0, 1 @ set context ID
252 .long 0x000f0000 @ Required ID value
253 .long 0x000f0000 @ Mask for ID
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| D | proc-v6.S | 106 mcr p15, 0, r1, c13, c0, 1 @ set context ID
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| D | Kconfig | 355 bool "Accept early Feroceon cores with an ARM926 ID"
360 for which the CPU ID is equal to the ARM926 ID.
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| /arch/mips/include/asm/pmc-sierra/msp71xx/ |
| D | msp_pci.h | 29 #define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220)) argument
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| /arch/arm/ |
| D | Kconfig-nommu | 29 hex 'Hard wire the processor ID'
33 If processor has no CP15 register, this processor ID is
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| /arch/arm/plat-s3c24xx/ |
| D | sleep.S | 68 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
152 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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| /arch/x86/include/asm/ |
| D | io_apic.h | 34 ID : 8; member
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| /arch/arm/mach-pxa/ |
| D | sleep.S | 31 mrc p15, 0, r6, c3, c0, 0 @ domain ID
72 mrc p15, 0, r6, c3, c0, 0 @ domain ID
120 mcr p15, 0, r6, c3, c0, 0 @ domain ID
350 mcr p15, 0, r6, c3, c0, 0 @ domain ID
|
| /arch/arm/mach-sa1100/ |
| D | sleep.S | 41 mrc p15, 0, r4, c3, c0, 0 @ domain ID
193 mcr p15, 0, r4, c3, c0, 0 @ domain ID
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| /arch/arm/kernel/ |
| D | head-common.S | 55 str r9, [r4] @ Save processor ID
89 mov r4, r1 @ preserve machine ID
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| /arch/x86/kernel/ |
| D | head_32.S | 379 xorl $0x240000,%eax # flip AC and ID bits in EFLAGS
391 testl $0x200000,%eax # check if ID bit changed
395 xorl %eax,%eax # call CPUID with 0 -> return vendor ID
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| D | io_apic.c | 1724 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); in print_IO_APIC()
2130 reg_00.bits.ID); in setup_ioapic_ids_from_mpc()
2131 mp_ioapics[apic].mp_apicid = reg_00.bits.ID; in setup_ioapic_ids_from_mpc()
2180 reg_00.bits.ID = mp_ioapics[apic].mp_apicid; in setup_ioapic_ids_from_mpc()
2191 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid) in setup_ioapic_ids_from_mpc()
3121 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { in ioapic_resume()
3122 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; in ioapic_resume()
3897 "%d\n", ioapic, apic_id, reg_00.bits.ID); in io_apic_get_unique_id()
3898 apic_id = reg_00.bits.ID; in io_apic_get_unique_id()
3924 if (reg_00.bits.ID != apic_id) { in io_apic_get_unique_id()
[all …]
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| /arch/mips/include/asm/mach-cavium-octeon/ |
| D | kernel-entry-init.h | 46 # Read the processor ID register
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| /arch/frv/kernel/ |
| D | entry-table.S | 37 # table, as indexed by the exception ID from the TBR.
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| /arch/powerpc/boot/dts/ |
| D | sbc8560.dts | 341 0x2 0x0 0x5 0x200000 0x1fff // ID reg.
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| D | sbc8641d.dts | 118 1 0 5 1 1 // Board ID/Rev
|
| /arch/cris/arch-v32/kernel/ |
| D | head.S | 166 ;; Read CPU ID
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| /arch/x86/ |
| D | Kconfig | 1852 to support platforms with CPU's having > 8 bit APIC ID, say Y.
|