Home
last modified time | relevance | path

Searched refs:LC0 (Results 1 – 18 of 18) sorted by relevance

/arch/blackfin/lib/
Douts.S39 LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
50 LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
61 LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
72 LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
Dmemcpy.S85 LSETUP(.Lthree_start, .Lthree_end) LC0=P2;
96 LSETUP(.Lword_loops, .Lword_loope) LC0=P2;
120 LSETUP (.Lbyte_start, .Lbyte_end) LC0=P2;
139 LSETUP(.Lover_start, .Lover_end) LC0=P2;
Dmemmove.S72 LSETUP (.Lquad_loops, .Lquad_loope) LC0=P1;
91 .Lbytes: LSETUP (.Lbyte2_s, .Lbyte2_e) LC0=P2;
109 LSETUP (.Lol_s, .Lol_e) LC0 = P2;
Dmemcmp.S62 LSETUP (.Lquad_loop_s, .Lquad_loop_e) LC0=P1;
81 LSETUP (.Lbyte_loop_s, .Lbyte_loop_e) LC0=P2;
Dmemset.S67 LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
86 LSETUP (.Lbyte_loop , .Lbyte_loop) LC0=P2;
Dmemchr.S52 LSETUP (.Lbyte_loop_s, .Lbyte_loop_e) LC0=P2;
Dins.S82 LSETUP(1f, 2f) LC0 = P2; \
Ddivsi3.S142 LSETUP(.Llst,.Llend) LC0 = P1; /* Setup loop */
Dudivsi3.S172 LSETUP(.Lulst, .Lulend) LC0 = P1; /* Set loop counter */
/arch/blackfin/include/asm/
Dcontext.S74 [--sp] = LC0;
141 [--sp] = LC0;
200 [--sp] = LC0;
262 LC0 = [sp++]; define
325 LC0 = [sp++]; define
370 [--sp] = LC0;
388 LC0 = [sp++]; define
/arch/arm/lib/
Ddelay.S15 .LC0: .word loops_per_jiffy label
28 ldr r2, .LC0
/arch/arm/boot/compressed/
Dll_char_wr.S24 LC0: .word LC0 label
47 adr ip, LC0
Dhead.S157 adr r0, LC0
288 .type LC0, #object
289 LC0: .word LC0 @ r1 label
298 .size LC0, . - LC0
/arch/blackfin/mach-common/
Dentry.S249 R7=LC0;
250 LC0=R7;
1015 [--sp] = LC0;
1025 LC0 = R7; define
1044 LSETUP (.Lstart, .Lend) LC0;
1057 LC0 = [sp++]; define
Dinterrupt.S85 [--sp] = LC0;
Dhead.S62 LC0 = r0; define
Ddpmc_modes.S534 [--sp] = LC0;
588 LC0 = [sp++]; define
/arch/blackfin/mach-bf561/
Dsecondary.S58 LC0 = r0; define