| /arch/arm/mach-shark/ |
| D | irq.c | 27 static unsigned char cached_irq_mask[2] = { 0xfb, 0xff }; variable
38 cached_irq_mask[0] |= mask; in shark_disable_8259A_irq()
39 outb(cached_irq_mask[1],0xA1); in shark_disable_8259A_irq()
42 cached_irq_mask[1] |= mask; in shark_disable_8259A_irq()
43 outb(cached_irq_mask[0],0x21); in shark_disable_8259A_irq()
52 cached_irq_mask[0] &= mask; in shark_enable_8259A_irq()
53 outb(cached_irq_mask[0],0x21); in shark_enable_8259A_irq()
56 cached_irq_mask[1] &= mask; in shark_enable_8259A_irq()
57 outb(cached_irq_mask[1],0xA1); in shark_enable_8259A_irq()
100 outb(cached_irq_mask[1],0xA1); in shark_init_irq()
[all …]
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| /arch/alpha/kernel/ |
| D | irq_pyxis.c | 21 static unsigned long cached_irq_mask; variable
34 pyxis_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16)); in pyxis_enable_irq()
40 pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16))); in pyxis_disable_irq()
61 unsigned long mask = cached_irq_mask &= ~bit; in pyxis_mask_and_ack_irq()
91 pld &= cached_irq_mask; in pyxis_device_interrupt()
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| D | sys_dp264.c | 41 static unsigned long cached_irq_mask; variable
104 cached_irq_mask |= 1UL << irq; in dp264_enable_irq()
105 tsunami_update_irq_hw(cached_irq_mask); in dp264_enable_irq()
113 cached_irq_mask &= ~(1UL << irq); in dp264_disable_irq()
114 tsunami_update_irq_hw(cached_irq_mask); in dp264_disable_irq()
136 cached_irq_mask |= 1UL << (irq - 16); in clipper_enable_irq()
137 tsunami_update_irq_hw(cached_irq_mask); in clipper_enable_irq()
145 cached_irq_mask &= ~(1UL << (irq - 16)); in clipper_disable_irq()
146 tsunami_update_irq_hw(cached_irq_mask); in clipper_disable_irq()
184 tsunami_update_irq_hw(cached_irq_mask); in dp264_set_affinity()
[all …]
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| D | sys_rx164.c | 36 static unsigned long cached_irq_mask; variable
52 rx164_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16)); in rx164_enable_irq()
58 rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16))); in rx164_disable_irq()
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| D | irq_i8259.c | 23 static unsigned int cached_irq_mask = 0xffff; variable
39 i8259_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq)); in i8259a_enable_irq()
46 i8259_update_irq_hw(irq, cached_irq_mask |= 1 << irq); in __i8259a_disable_irq()
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| D | sys_wildfire.c | 33 static unsigned long cached_irq_mask[WILDFIRE_NR_IRQS/(sizeof(long)*8)]; variable
60 *enable0 = cached_irq_mask[qbbno * WILDFIRE_PCA_PER_QBB + pcano]; in wildfire_update_irq_hw()
113 set_bit(irq, &cached_irq_mask); in wildfire_enable_irq()
125 clear_bit(irq, &cached_irq_mask); in wildfire_disable_irq()
137 clear_bit(irq, &cached_irq_mask); in wildfire_mask_and_ack_irq()
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| D | sys_eb64p.c | 38 static unsigned int cached_irq_mask = -1; variable
49 eb64p_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq)); in eb64p_enable_irq()
55 eb64p_update_irq_hw(irq, cached_irq_mask |= 1 << irq); in eb64p_disable_irq()
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| D | sys_mikasa.c | 37 static int cached_irq_mask; variable
48 mikasa_update_irq_hw(cached_irq_mask |= 1 << (irq - 16)); in mikasa_enable_irq()
54 mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16))); in mikasa_disable_irq()
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| D | sys_eiger.c | 41 static unsigned long cached_irq_mask[2] = { -1, -1 }; variable
57 mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63))); in eiger_enable_irq()
65 mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63)); in eiger_disable_irq()
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| D | sys_takara.c | 35 static unsigned long cached_irq_mask[2] = { -1, -1 }; variable
51 mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63))); in takara_enable_irq()
59 mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63)); in takara_disable_irq()
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| D | sys_alcor.c | 37 static unsigned long cached_irq_mask; variable
49 alcor_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16)); in alcor_enable_irq()
55 alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16))); in alcor_disable_irq()
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| D | sys_noritake.c | 37 static int cached_irq_mask; variable
53 noritake_update_irq_hw(irq, cached_irq_mask |= 1 << (irq - 16)); in noritake_enable_irq()
59 noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16))); in noritake_disable_irq()
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| D | sys_cabriolet.c | 39 static unsigned long cached_irq_mask = ~0UL; variable
51 cabriolet_update_irq_hw(irq, cached_irq_mask &= ~(1UL << irq)); in cabriolet_enable_irq()
57 cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq); in cabriolet_disable_irq()
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| /arch/xtensa/kernel/ |
| D | irq.c | 25 static unsigned int cached_irq_mask; variable
125 cached_irq_mask &= ~(1 << irq); in xtensa_irq_mask()
126 set_sr (cached_irq_mask, INTENABLE); in xtensa_irq_mask()
131 cached_irq_mask |= 1 << irq; in xtensa_irq_unmask()
132 set_sr (cached_irq_mask, INTENABLE); in xtensa_irq_unmask()
185 cached_irq_mask = 0; in init_IRQ()
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| /arch/x86/include/asm/ |
| D | i8259.h | 6 extern unsigned int cached_irq_mask;
9 #define cached_master_mask (__byte(0, cached_irq_mask))
10 #define cached_slave_mask (__byte(1, cached_irq_mask))
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| /arch/mips/kernel/ |
| D | i8259.c | 56 static unsigned int cached_irq_mask = 0xffff; variable
58 #define cached_master_mask (cached_irq_mask)
59 #define cached_slave_mask (cached_irq_mask >> 8)
69 cached_irq_mask |= mask; in disable_8259A_irq()
85 cached_irq_mask &= mask; in enable_8259A_irq()
170 if (cached_irq_mask & irqmask) in mask_and_ack_8259A()
172 cached_irq_mask |= irqmask; in mask_and_ack_8259A()
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| /arch/x86/kernel/ |
| D | i8259.c | 54 unsigned int cached_irq_mask = 0xffff; variable
73 cached_irq_mask |= mask; in disable_8259A_irq()
87 cached_irq_mask &= mask; in enable_8259A_irq()
170 if (cached_irq_mask & irqmask) in mask_and_ack_8259A()
172 cached_irq_mask |= irqmask; in mask_and_ack_8259A()
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| D | visws_quirks.c | 615 cached_irq_mask |= 1 << realirq; in piix4_master_intr()
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