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Searched refs:control (Results 1 – 25 of 136) sorted by relevance

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/arch/powerpc/boot/
Dmv64x60_i2c.c75 static int mv64x60_i2c_control(int control, int status) in mv64x60_i2c_control() argument
77 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); in mv64x60_i2c_control()
81 static int mv64x60_i2c_read_byte(int control, int status) in mv64x60_i2c_read_byte() argument
83 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); in mv64x60_i2c_read_byte()
89 static int mv64x60_i2c_write_byte(int data, int control, int status) in mv64x60_i2c_write_byte() argument
92 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); in mv64x60_i2c_write_byte()
101 int control; in mv64x60_i2c_read() local
118 control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN; in mv64x60_i2c_read()
120 if (mv64x60_i2c_control(control, status) < 0) in mv64x60_i2c_read()
125 control = MV64x60_I2C_CONTROL_TWSIEN; in mv64x60_i2c_read()
[all …]
/arch/arm/mach-rpc/include/mach/
Dacornfb.h98 case 1: vidc->control |= VIDC20_CTRL_PIX_CK; break; in acornfb_vidc20_find_rates()
99 case 2: vidc->control |= VIDC20_CTRL_PIX_CK2; break; in acornfb_vidc20_find_rates()
100 case 3: vidc->control |= VIDC20_CTRL_PIX_CK3; break; in acornfb_vidc20_find_rates()
101 case 4: vidc->control |= VIDC20_CTRL_PIX_CK4; break; in acornfb_vidc20_find_rates()
102 case 5: vidc->control |= VIDC20_CTRL_PIX_CK5; break; in acornfb_vidc20_find_rates()
103 case 6: vidc->control |= VIDC20_CTRL_PIX_CK6; break; in acornfb_vidc20_find_rates()
104 case 7: vidc->control |= VIDC20_CTRL_PIX_CK7; break; in acornfb_vidc20_find_rates()
105 case 8: vidc->control |= VIDC20_CTRL_PIX_CK8; break; in acornfb_vidc20_find_rates()
118 vidc->control |= VIDC20_CTRL_FIFO_24; in acornfb_vidc20_find_rates()
120 vidc->control |= VIDC20_CTRL_FIFO_28; in acornfb_vidc20_find_rates()
[all …]
/arch/mips/oprofile/
Dop_model_rm9000.c32 unsigned int control; member
41 unsigned int control = 0; in rm9000_reg_setup() local
46 control |= RM9K_COUNTER1_EVENT(ctr[0].event) | in rm9000_reg_setup()
51 control |= RM9K_COUNTER2_EVENT(ctr[1].event) | in rm9000_reg_setup()
55 reg.control = control; in rm9000_reg_setup()
74 write_c0_perfcontrol(reg.control); in rm9000_cpu_start()
85 unsigned int control = read_c0_perfcontrol(); in rm9000_perfcount_handler() local
102 if (control & RM9K_COUNTER1_OVERFLOW) { in rm9000_perfcount_handler()
106 if (control & RM9K_COUNTER2_OVERFLOW) { in rm9000_perfcount_handler()
113 write_c0_perfcontrol(reg.control); in rm9000_perfcount_handler()
Dop_model_mipsxx.c128 unsigned int control[4]; member
141 reg.control[i] = 0; in mipsxx_reg_setup()
147 reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) | in mipsxx_reg_setup()
150 reg.control[i] |= M_PERFCTL_KERNEL; in mipsxx_reg_setup()
152 reg.control[i] |= M_PERFCTL_USER; in mipsxx_reg_setup()
154 reg.control[i] |= M_PERFCTL_EXL; in mipsxx_reg_setup()
188 w_c0_perfctrl3(WHAT | reg.control[3]); in mipsxx_cpu_start()
190 w_c0_perfctrl2(WHAT | reg.control[2]); in mipsxx_cpu_start()
192 w_c0_perfctrl1(WHAT | reg.control[1]); in mipsxx_cpu_start()
194 w_c0_perfctrl0(WHAT | reg.control[0]); in mipsxx_cpu_start()
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/arch/sparc/kernel/
Dpsycho_common.c37 u64 control; in psycho_check_stc_error() local
57 control = upa_readq(strbuf->strbuf_control); in psycho_check_stc_error()
58 upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control); in psycho_check_stc_error()
74 upa_writeq(control, strbuf->strbuf_control); in psycho_check_stc_error()
205 u64 control, iommu_tag[16], iommu_data[16]; in psycho_check_iommu_error() local
210 control = upa_readq(iommu->iommu_control); in psycho_check_iommu_error()
211 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) { in psycho_check_iommu_error()
214 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR; in psycho_check_iommu_error()
215 upa_writeq(control, iommu->iommu_control); in psycho_check_iommu_error()
217 switch ((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) { in psycho_check_iommu_error()
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Dsbus.c496 u64 control; in sysio_register_error_handlers() local
531 control = upa_readq(iommu->write_complete_reg); in sysio_register_error_handlers()
532 control |= 0x100UL; /* SBUS Error Interrupt Enable */ in sysio_register_error_handlers()
533 upa_writeq(control, iommu->write_complete_reg); in sysio_register_error_handlers()
545 u64 control; in sbus_iommu_init() local
600 control = upa_readq(iommu->iommu_control); in sbus_iommu_init()
601 control = ((7UL << 16UL) | in sbus_iommu_init()
605 upa_writeq(control, iommu->iommu_control); in sbus_iommu_init()
627 control = (1UL << 1UL) | (1UL << 0UL); in sbus_iommu_init()
628 upa_writeq(control, strbuf->strbuf_control); in sbus_iommu_init()
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Dpci_schizo.c131 u64 control; in __schizo_check_stc_error_pbm() local
149 control = upa_readq(strbuf->strbuf_control); in __schizo_check_stc_error_pbm()
150 upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB), in __schizo_check_stc_error_pbm()
167 upa_writeq(control, strbuf->strbuf_control); in __schizo_check_stc_error_pbm()
240 u64 control; in schizo_check_iommu_error_pbm() local
244 control = upa_readq(iommu->iommu_control); in schizo_check_iommu_error_pbm()
245 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) { in schizo_check_iommu_error_pbm()
250 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR; in schizo_check_iommu_error_pbm()
251 upa_writeq(control, iommu->iommu_control); in schizo_check_iommu_error_pbm()
253 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) { in schizo_check_iommu_error_pbm()
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Dpci_psycho.c425 u64 control; in psycho_pbm_strbuf_init() local
463 control = upa_readq(pbm->stc.strbuf_control); in psycho_pbm_strbuf_init()
464 control |= PSYCHO_STRBUF_CTRL_ENAB; in psycho_pbm_strbuf_init()
465 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR); in psycho_pbm_strbuf_init()
467 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS); in psycho_pbm_strbuf_init()
470 control |= PSYCHO_STRBUF_CTRL_RRDIS; in psycho_pbm_strbuf_init()
473 upa_writeq(control, pbm->stc.strbuf_control); in psycho_pbm_strbuf_init()
/arch/arm/mach-sa1100/include/mach/
Dh3600.h98 void (*control)(enum ipaq_egpio_type, int); member
114 if (ipaq_model_ops.control) in assign_h3600_egpio()
115 ipaq_model_ops.control(x,level); in assign_h3600_egpio()
120 if (ipaq_model_ops.control) in clr_h3600_egpio()
121 ipaq_model_ops.control(x,0); in clr_h3600_egpio()
126 if (ipaq_model_ops.control) in set_h3600_egpio()
127 ipaq_model_ops.control(x,1); in set_h3600_egpio()
/arch/mips/pci/
Dops-mace.c45 u32 control = mace->pci.control; in mace_pci_read_config() local
48 mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT; in mace_pci_read_config()
63 mace->pci.control = control; in mace_pci_read_config()
Dpci-rc32434.c160 rc32434_pci->pcilba[0].control = in rc32434_pcibridge_init()
162 dummyread = rc32434_pci->pcilba[0].control; /* flush the CPU write Buffers */ in rc32434_pcibridge_init()
167 rc32434_pci->pcilba[1].control = in rc32434_pcibridge_init()
169 dummyread = rc32434_pci->pcilba[1].control; /* flush the CPU write Buffers */ in rc32434_pcibridge_init()
174 rc32434_pci->pcilba[2].control = in rc32434_pcibridge_init()
176 dummyread = rc32434_pci->pcilba[2].control; /* flush the CPU write Buffers */ in rc32434_pcibridge_init()
181 rc32434_pci->pcilba[3].control = in rc32434_pcibridge_init()
184 dummyread = rc32434_pci->pcilba[3].control; /* flush the CPU write Buffers */ in rc32434_pcibridge_init()
/arch/x86/kvm/
Dsvm.c210 svm->vmcb->control.event_inj = nr in svm_queue_exception()
214 svm->vmcb->control.event_inj_err = error_code; in svm_queue_exception()
221 return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID); in svm_exception_injected()
243 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; in skip_emulated_instruction()
382 svm->vmcb->control.lbr_ctl = 1; in svm_enable_lbrv()
393 svm->vmcb->control.lbr_ctl = 0; in svm_disable_lbrv()
480 struct vmcb_control_area *control = &svm->vmcb->control; in init_vmcb() local
483 control->intercept_cr_read = INTERCEPT_CR0_MASK | in init_vmcb()
487 control->intercept_cr_write = INTERCEPT_CR0_MASK | in init_vmcb()
492 control->intercept_dr_read = INTERCEPT_DR0_MASK | in init_vmcb()
[all …]
/arch/um/drivers/
Ddaemon_user.c56 pri->control = socket(AF_UNIX, SOCK_STREAM, 0); in connect_to_switch()
57 if (pri->control < 0) { in connect_to_switch()
64 if (connect(pri->control, (struct sockaddr *) ctl_addr, in connect_to_switch()
98 n = write(pri->control, &req, sizeof(req)); in connect_to_switch()
106 n = read(pri->control, sun, sizeof(*sun)); in connect_to_switch()
122 close(pri->control); in connect_to_switch()
167 close(pri->control); in daemon_remove()
168 pri->control = -1; in daemon_remove()
/arch/m68k/hp300/
Dhp300map.map6 # altgr control keycode 83 = Boot
7 # altgr control keycode 111 = Boot
78 control keycode 63 = nul
90 control keycode 73 = Console_4
92 control keycode 74 = Console_3
94 control keycode 75 = Console_2
96 control keycode 76 = Console_1
102 control keycode 81 = Console_5
104 control keycode 82 = Console_6
106 control keycode 83 = Console_7
[all …]
/arch/avr32/mach-at32ap/
Dat32ap700x.c109 static unsigned long pll_get_rate(struct clk *clk, unsigned long control) in pll_get_rate() argument
113 div = PM_BFEXT(PLLDIV, control) + 1; in pll_get_rate()
114 mul = PM_BFEXT(PLLMUL, control) + 1; in pll_get_rate()
190 u32 control; in pll0_get_rate() local
192 control = pm_readl(PLL0); in pll0_get_rate()
194 return pll_get_rate(clk, control); in pll0_get_rate()
234 u32 control; in pll1_get_rate() local
236 control = pm_readl(PLL1); in pll1_get_rate()
238 return pll_get_rate(clk, control); in pll1_get_rate()
365 u32 control; in cpu_clk_set_rate() local
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/arch/powerpc/include/asm/
Ddbdma.h15 unsigned int control; /* lets you change bits in status */ member
96 out_le32(&((regs)->control), (RUN|FLUSH)<<16); \
102 out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
/arch/arm/boot/compressed/
Dbig-endian.S10 mrc p15, 0, r0, c1, c0, 0 @ read control reg
12 mcr p15, 0, r0, c1, c0, 0 @ write control reg
/arch/mips/pmc-sierra/yosemite/
Dsetup.c80 m48t37_base->control = 0x40; in read_persistent_clock()
92 m48t37_base->control = 0x00; in read_persistent_clock()
113 m48t37_base->control = 0x80; in rtc_mips_set_time()
134 m48t37_base->control = 0x00; in rtc_mips_set_time()
/arch/mips/include/asm/ip32/
Dmace.h49 volatile unsigned int control; member
135 volatile unsigned long control; member
140 volatile unsigned long control; /* channel control */ member
240 volatile unsigned long control; member
259 volatile unsigned long control; member
/arch/x86/kernel/
Dearly_printk.c236 ctrl = readl(&ehci_debug->control); in dbgp_wait_until_complete()
249 writel(ctrl | DBGP_DONE, &ehci_debug->control); in dbgp_wait_until_complete()
275 writel(ctrl | DBGP_GO, &ehci_debug->control); in dbgp_wait_until_done()
342 ctrl = readl(&ehci_debug->control); in dbgp_bulk_write()
372 ctrl = readl(&ehci_debug->control); in dbgp_bulk_read()
411 ctrl = readl(&ehci_debug->control); in dbgp_control_msg()
643 ctrl = readl(&ehci_debug->control); in ehci_setup()
646 writel(ctrl, &ehci_debug->control); in ehci_setup()
678 ctrl = readl(&ehci_debug->control); in ehci_setup()
680 writel(ctrl, &ehci_debug->control); in ehci_setup()
[all …]
/arch/mips/include/asm/mach-cavium-octeon/
Dkernel-entry-init.h30 # Read the cavium mem control register
35 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
36 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
66 # Write the cavium control register
/arch/blackfin/kernel/
Dipipe.c104 if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control))) in __ipipe_handle_irq()
109 if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) { in __ipipe_handle_irq()
124 if (test_bit(IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) { in __ipipe_handle_irq()
131 if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control)) in __ipipe_handle_irq()
/arch/ia64/kernel/
Dpalinfo.c534 feature_set_info(char *page, u64 avail, u64 status, u64 control, u64 set) in feature_set_info() argument
541 for(i=0; i < 64; i++, avail >>=1, status >>=1, control >>=1) { in feature_set_info()
543 if (!(control)) /* No remaining bits set */ in feature_set_info()
553 avail & 0x1 ? (control & 0x1 ? in feature_set_info()
561 avail & 0x1 ? (control & 0x1 ? in feature_set_info()
572 u64 avail=1, status=1, control=1, feature_set=0; in processor_info() local
576 ret = ia64_pal_proc_get_features(&avail, &status, &control, in processor_info()
586 p = feature_set_info(p, avail, status, control, feature_set); in processor_info()
626 u64 avail, status, control; in bus_info() local
634 control = ct.pal_bus_features_val; in bus_info()
[all …]
/arch/arm/kernel/
Dhead-nommu.S62 mrc p15, 0, r0, c1, c0, 0 @ read control reg
82 mcr p15, 0, r0, c1, c0, 0 @ write control reg
/arch/s390/kernel/
Dhead31.S20 lctl %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
44 .long .Lduct # cr2: dispatchable unit control table
86 # check control registers

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