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Searched refs:ldr (Results 1 – 25 of 129) sorted by relevance

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/arch/arm/mach-omap2/
Dsram34xx.S64 ldr r4, omap3_sdrc_dlla_ctrl
65 ldr r5, [r4]
70 ldr r4, omap3_sdrc_dlla_ctrl
71 ldr r5, [r4]
78 ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
79 ldr r5, [r4] @ read the contents of SDRC_POWER
82 ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
83 ldr r5, [r4]
87 ldr r4, omap3_cm_idlest1_core
88 ldr r5, [r4]
[all …]
Dsram243x.S43 ldr r2, omap243x_sdi_cm_clksel2_pll @ get address of dpllout reg
52 ldr r11, omap243x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
53 ldr r10, [r11] @ get current val
65 ldr r10, [r11] @ get locked value
103 ldr r4, omap243x_sdi_prcm_voltctrl @ get addr of volt ctrl.
104 ldr r5, [r4] @ get value.
105 ldr r6, prcm_mask_val @ get value of mask
113 ldr r3, omap243x_sdi_timer_32ksynct_cr @ get addr of counter
114 ldr r5, [r3] @ get value
117 ldr r7, [r3] @ get timer value
[all …]
Dsram242x.S43 ldr r2, omap242x_sdi_cm_clksel2_pll @ get address of dpllout reg
52 ldr r11, omap242x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
53 ldr r10, [r11] @ get current val
65 ldr r10, [r11] @ get locked value
103 ldr r4, omap242x_sdi_prcm_voltctrl @ get addr of volt ctrl.
104 ldr r5, [r4] @ get value.
105 ldr r6, prcm_mask_val @ get value of mask
113 ldr r3, omap242x_sdi_timer_32ksynct_cr @ get addr of counter
114 ldr r5, [r3] @ get value
117 ldr r7, [r3] @ get timer value
[all …]
/arch/arm/lib/
Dio-readsw-armv3.S25 ldr r3, [r0]
46 .Linsw_8_lp: ldr r3, [r0]
48 ldr r4, [r0]
51 ldr r4, [r0]
53 ldr r5, [r0]
56 ldr r5, [r0]
58 ldr r6, [r0]
61 ldr r6, [r0]
63 ldr lr, [r0]
77 ldr r3, [r0]
[all …]
Dbacktrace.S45 ldr r0, [sp], #4 @ by stmfd for this CPU
67 1001: ldr sv_pc, [frame, #0] @ get saved pc
68 1002: ldr sv_fp, [frame, #-12] @ get saved fp
73 1003: ldr r2, [sv_pc, #-4] @ if stmfd sp!, {args} exists,
74 ldr r3, .Ldsi+4 @ adjust saved 'pc' back one
79 ldr r1, [frame, #-4] @ get saved lr
84 ldr r1, [sv_pc, #-4] @ if stmfd sp!, {args} exists,
85 ldr r3, .Ldsi+4
91 1004: ldr r1, [sv_pc, #0] @ if stmfd sp!, {..., fp, ip, lr, pc}
92 ldr r3, .Ldsi @ instruction exists,
[all …]
Dsha1.S61 2: ldr r4, [r3, #4]!
63 ldr r5, [r3, #8]
64 ldr r6, [r3, #32]
65 ldr r7, [r3, #52]
95 ldr r3, [r2], #4
106 ldr r3, [r2], #4
116 ldr r3, [r2], #4
130 ldr r1, .L_sha_K + 0
145 ldr r1, .L_sha_K + 4
156 ldr r1, .L_sha_K + 8
[all …]
/arch/arm/mach-at91/
Dpm_slowclock.S59 ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
73 ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
87 ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
101 ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
120 ldr r1, .at91_va_base_pmc
121 ldr r2, .at91_va_base_sdramc
132 ldr r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
139 ldr r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
147 ldr r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
171 ldr r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
[all …]
/arch/arm/mach-pxa/
Dstandby.S23 ldr r0, =PSSR
27 ldr ip, [r3]
63 ldr r2, [r1] @ Dummy read PXA3_MDCNFG
70 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
73 1: ldr r0, [r1, #PXA3_DDR_HCAL]
77 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
84 ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
88 ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
93 1: ldr r0, [r1, #PXA3_DMCISR]
97 ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
[all …]
Dsleep.S49 ldr r1, =sleep_save_sp
51 ldr pc, [sp], #4
86 ldr r1, =sleep_save_sp
108 ldr r0, sleep_save_sp @ stack phys addr
129 ldr r2, =0x542e
134 ldr r5, [r1, r3, lsl #2]
140 ldr r8, [r1, r6, lsl #2]
143 ldr r2, =pxa3xx_resume_after_mmu @ absolute virtual address
189 ldr r4, =MDREFR
190 ldr r5, [r4]
[all …]
/arch/arm/mach-mv78xx0/include/mach/
Dentry-macro.S20 ldr \base, =IRQ_VIRT_BASE
25 ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
26 ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
32 ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
33 ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF]
39 ldr \irqstat, [\base, #IRQ_CAUSE_ERR_OFF]
40 ldr \tmp, [\base, #IRQ_MASK_ERR_OFF]
/arch/arm/boot/compressed/
Dhead-sharpsl.S27 ldr r7, .TOSAID
37 ldr r3, .PXA270ID
42 ldr r1, .W100ADDR @ Base address of w100 chip + regs offset
53 ldr r6, [r1, #0] @ Load Chip ID
54 ldr r3, .W100ID
55 ldr r7, .POODLEID
60 ldr r7, .CORGIID
61 ldr r3, .PXA255ID
67 ldr r7, .SHEPHERDID
72 ldr r7, .HUSKYID @ Must be Husky
[all …]
/arch/arm/plat-omap/include/mach/
Dentry-macro.S40 ldr \base, =IO_ADDRESS(OMAP_IH1_BASE)
41 ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
42 ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET]
48 ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
81 ldr \base, =OMAP2_VA_IC_BASE
82 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
85 ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
88 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
/arch/arm/mach-sa1100/
Dsleep.S53 ldr r1, =sleep_save_sp
65 ldr r0, =MDREFR
66 ldr r1, [r0]
74 ldr r0, =PPCR
99 ldr r0, =MSC0
100 ldr r1, =MSC1
101 ldr r2, =MSC2
103 ldr r3, [r0]
107 ldr r4, [r1]
111 ldr r5, [r2]
[all …]
/arch/arm/kernel/
Drelocate_kernel.S10 ldr r0,kexec_indirection_page
11 ldr r1,kexec_start_address
15 ldr r3, [r0],#4
42 ldr r5,[r3],#4
52 ldr r1,kexec_mach_type
53 ldr r2,kexec_boot_atags
Dentry-common.S26 ldr r1, [tsk, #TI_FLAGS]
34 ldr r1, [sp, #S_OFF + S_PSR] @ get calling cpsr
35 ldr lr, [sp, #S_OFF + S_PC]! @ get pc
65 ldr r1, [tsk, #TI_FLAGS]
73 ldr r1, [sp, #S_PSR] @ get calling cpsr
74 ldr lr, [sp, #S_PC]! @ get pc
88 ldr r1, [tsk, #TI_FLAGS] @ check for syscall tracing
114 ldr lr, [fp, #-4] @ restore lr
119 ldr r1, [fp, #-4]
126 ldr lr, [fp, #-4] @ restore lr
[all …]
Dcrunch-bits.S68 ldr r8, =(EP93XX_APB_VIRT_BASE + 0x00130000) @ syscon addr
70 ldr r1, [r8, #0x80]
78 ldr r3, =crunch_owner
80 ldr r2, [sp, #60] @ current task pc value
81 ldr r1, [r3] @ get current crunch owner
86 ldr r2, [r8, #0x80]
208 ldr r4, =(EP93XX_APB_VIRT_BASE + 0x00130000) @ syscon addr
210 ldr r3, =crunch_owner
212 ldr r1, [r3] @ get current crunch owner
219 ldr r5, [r4, #0x80] @ enable access to crunch
[all …]
/arch/arm/vfp/
Dentry.S24 ldr r4, [r10, #TI_PREEMPT] @ get preempt count
29 ldr r4, .LCvfp
30 ldr r11, [r10, #TI_CPU] @ CPU number
32 ldr pc, [r4] @ call VFP entry point
38 ldr r4, [r10, #TI_PREEMPT] @ get preempt count
55 ldr r4, [r10, #TI_PREEMPT] @ get preempt count
59 ldr r0, VFP_arch_address
/arch/arm/mach-kirkwood/include/mach/
Dentry-macro.S20 ldr \base, =IRQ_VIRT_BASE
25 ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
26 ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
32 ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
33 ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF]
/arch/arm/mach-s3c2410/
Dsleep.S45 ldr r4, =S3C2410_REFRESH
46 ldr r5, =S3C24XX_MISCCR
47 ldr r6, =S3C2410_CLKCON
48 ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB)
49 ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB)
50 ldr r9, [ r6 ] @ get CLKCON (and ensure in TLB)
/arch/arm/plat-s3c/include/plat/
Ddebug-macro.S18 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
27 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
40 ldr \rd, [ \rx, # S3C2410_UFCON ]
51 ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
59 ldr \rd, [ \rx, # S3C2410_UFCON ]
70 ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
/arch/arm/mach-ixp4xx/include/mach/
Dentry-macro.S22 ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
23 ldr \irqstat, [\irqstat] @ get interrupts
37 ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
38 ldr \irqstat, [\irqstat] @ get upper interrupts
/arch/arm/mach-pnx4008/include/mach/
Dentry-macro.S39 ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
40 ldr \irqstat, [\base, #INTRC_STAT]
76 ldr \irqstat, [\base, #INTRC_STAT]
77 ldr \tmp, [\base, #INTRC_TYPE]
92 ldr \irqstat, [\base, #INTRC_STAT]
93 ldr \tmp, [\base, #INTRC_TYPE]
/arch/arm/mach-realview/include/mach/
Dentry-macro.S17 ldr \base, =gic_cpu_base_addr
18 ldr \base, [\base]
45 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
47 ldr \tmp, =1021
/arch/arm/mach-goldfish/include/mach/
Dentry-macro.S29 ldr \base, =IO_ADDRESS(GOLDFISH_INTERRUPT_BASE)
30 ldr \irqnr, [\base, #GOLDFISH_INTERRUPT_NUMBER]
31 ldr \irqstat, [\base, #GOLDFISH_INTERRUPT_STATUS]
/arch/arm/mach-loki/include/mach/
Dentry-macro.S20 ldr \base, =IRQ_VIRT_BASE
24 ldr \irqstat, [\base, #IRQ_CAUSE_OFF]
25 ldr \tmp, [\base, #IRQ_MASK_OFF]

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