| /arch/mips/include/asm/sgi/ |
| D | mc.h | 17 u32 _unused0;
18 volatile u32 cpuctrl0; /* CPU control register 0, readwrite */
38 u32 _unused1;
39 volatile u32 cpuctrl1; /* CPU control register 1, readwrite */
48 u32 _unused2;
49 volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */
51 u32 _unused3;
52 volatile u32 systemid; /* MC system ID register, readonly */
56 u32 _unused4[3];
57 volatile u32 divider; /* Divider reg for RPSS */
[all …]
|
| D | hpc3.h | 20 u32 pbuf; /* physical address of data buffer */
21 u32 cntinfo; /* counter and info bits */
33 u32 pnext; /* paddr of next hpc_dma_desc if any */
38 volatile u32 pbdma_bptr; /* pbus dma channel buffer ptr */
39 volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */
40 u32 _unused0[0x1000/4 - 2]; /* padding */
41 volatile u32 pbdma_ctrl; /* pbus dma channel control register has
58 u32 _unused1[0x1000/4 - 1]; /* padding */
63 volatile u32 cbptr; /* current dma buffer ptr, diagnostic use only */
64 volatile u32 ndptr; /* next dma descriptor ptr */
[all …]
|
| /arch/arm/plat-omap/include/mach/ |
| D | sram.h | 16 extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
18 extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
19 u32 base_cs, u32 force_unlock);
20 extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
21 u32 mem_type);
22 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
24 extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
25 u32 sdrc_actim_ctrla,
26 u32 sdrc_actim_ctrlb, u32 m2);
29 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
[all …]
|
| /arch/arm/include/asm/hardware/ |
| D | iop3xx.h | 46 #define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
57 #define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
62 #define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
63 #define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
64 #define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
65 #define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
66 #define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
67 #define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
70 #define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
75 #define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
[all …]
|
| /arch/powerpc/include/asm/ |
| D | immap_cpm2.h | 18 u32 sc_siumcr;
19 u32 sc_sypcr;
23 u32 sc_bcr;
26 u32 sc_ppc_alrh;
27 u32 sc_ppc_alrl;
30 u32 sc_lcl_alrh;
31 u32 sc_lcl_alrl;
32 u32 sc_tescr1;
33 u32 sc_tescr2;
34 u32 sc_ltescr1;
[all …]
|
| D | mpc52xx.h | 37 u32 mbar; /* MMAP_CTRL + 0x00 */
39 u32 cs0_start; /* MMAP_CTRL + 0x04 */
40 u32 cs0_stop; /* MMAP_CTRL + 0x08 */
41 u32 cs1_start; /* MMAP_CTRL + 0x0c */
42 u32 cs1_stop; /* MMAP_CTRL + 0x10 */
43 u32 cs2_start; /* MMAP_CTRL + 0x14 */
44 u32 cs2_stop; /* MMAP_CTRL + 0x18 */
45 u32 cs3_start; /* MMAP_CTRL + 0x1c */
46 u32 cs3_stop; /* MMAP_CTRL + 0x20 */
47 u32 cs4_start; /* MMAP_CTRL + 0x24 */
[all …]
|
| D | kvm_host.h | 44 u32 remote_tlb_flush;
48 u32 sum_exits;
49 u32 mmio_exits;
50 u32 dcr_exits;
51 u32 signal_exits;
52 u32 light_exits;
54 u32 itlb_real_miss_exits;
55 u32 itlb_virt_miss_exits;
56 u32 dtlb_real_miss_exits;
57 u32 dtlb_virt_miss_exits;
[all …]
|
| D | cell-pmu.h | 79 extern u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);
80 extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
81 extern u32 cbe_read_ctr(u32 cpu, u32 ctr);
82 extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
84 extern u32 cbe_read_pm07_control(u32 cpu, u32 ctr);
85 extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
86 extern u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg);
87 extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
89 extern u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr);
90 extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
[all …]
|
| D | pmac_pfunc.h | 25 u32 v;
26 u32 *p;
66 int (*write_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask);
67 int (*read_reg32)(PMF_STD_ARGS, u32 offset);
68 int (*write_reg16)(PMF_STD_ARGS, u32 offset, u16 value, u16 mask);
69 int (*read_reg16)(PMF_STD_ARGS, u32 offset);
70 int (*write_reg8)(PMF_STD_ARGS, u32 offset, u8 value, u8 mask);
71 int (*read_reg8)(PMF_STD_ARGS, u32 offset);
73 int (*delay)(PMF_STD_ARGS, u32 duration);
75 int (*wait_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask);
[all …]
|
| D | ps3av.h | 359 u32 cid; /* command id */
365 u32 cid;
366 u32 status;
372 u32 event_bit;
379 u32 reserved;
386 u32 status;
395 u32 res_bits;
396 u32 native;
415 u32 gamma;
454 u32 event_bit; /* in */
[all …]
|
| /arch/s390/include/asm/ |
| D | fcx.h | 37 u32 format:2;
38 u32 :6;
39 u32 flags:24;
40 u32 :8;
41 u32 tccbl:6;
42 u32 r:1;
43 u32 w:1;
44 u32 :16;
49 u32 output_count;
50 u32 input_count;
[all …]
|
| D | kvm_host.h | 106 u32 exit_userspace;
107 u32 exit_null;
108 u32 exit_external_request;
109 u32 exit_external_interrupt;
110 u32 exit_stop_request;
111 u32 exit_validity;
112 u32 exit_instruction;
113 u32 instruction_lctl;
114 u32 instruction_lctlg;
115 u32 exit_program_interruption;
[all …]
|
| /arch/mips/include/asm/mach-rc32434/ |
| D | eth.h | 36 u32 ethintfc;
37 u32 ethfifott;
38 u32 etharc;
39 u32 ethhash0;
40 u32 ethhash1;
41 u32 ethu0[4]; /* Reserved. */
42 u32 ethpfs;
43 u32 ethmcp;
44 u32 eth_u1[10]; /* Reserved. */
45 u32 ethspare;
[all …]
|
| /arch/mips/include/asm/txx9/ |
| D | tx4927pcic.h | 16 u32 pciid;
17 u32 pcistatus;
18 u32 pciccrev;
19 u32 pcicfg1;
20 u32 p2gm0plbase; /* +10 */
21 u32 p2gm0pubase;
22 u32 p2gm1plbase;
23 u32 p2gm1pubase;
24 u32 p2gm2pbase; /* +20 */
25 u32 p2giopbase;
[all …]
|
| /arch/x86/include/asm/ |
| D | apicdef.h | 160 #define u32 unsigned int macro
164 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
166 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
169 u32 __reserved_1 : 24,
172 u32 __reserved[3];
177 u32 version : 8,
181 u32 __reserved[3];
184 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
186 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
188 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
[all …]
|
| /arch/x86/kvm/ |
| D | tss.h | 5 u32 prev_task_link;
6 u32 esp0;
7 u32 ss0;
8 u32 esp1;
9 u32 ss1;
10 u32 esp2;
11 u32 ss2;
12 u32 cr3;
13 u32 eip;
14 u32 eflags;
[all …]
|
| /arch/mips/include/asm/sn/ |
| D | ioc3.h | 71 volatile u32 pad0[7]; /* 0x00000 */
72 volatile u32 sio_ir; /* 0x0001c */
73 volatile u32 sio_ies; /* 0x00020 */
74 volatile u32 sio_iec; /* 0x00024 */
75 volatile u32 sio_cr; /* 0x00028 */
76 volatile u32 int_out; /* 0x0002c */
77 volatile u32 mcr; /* 0x00030 */
80 volatile u32 gpcr_s; /* 0x00034 */
81 volatile u32 gpcr_c; /* 0x00038 */
82 volatile u32 gpdr; /* 0x0003c */
[all …]
|
| /arch/mips/include/asm/mach-au1x00/ |
| D | au1xxx_dbdma.h | 49 u32 ddma_config;
50 u32 ddma_intstat;
51 u32 ddma_throttle;
52 u32 ddma_inten;
64 u32 ddma_cfg; /* See below */
65 u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
66 u32 ddma_statptr; /* word aligned pointer to status word */
67 u32 ddma_dbell; /* A write activates channel operation */
68 u32 ddma_irq; /* If bit 0 set, interrupt pending */
69 u32 ddma_stat; /* See below */
[all …]
|
| /arch/ia64/sn/include/xtalk/ |
| D | xwidgetdev.h | 28 u32 w_id; /* 0x04 */
29 u32 w_pad_0; /* 0x00 */
30 u32 w_status; /* 0x0c */
31 u32 w_pad_1; /* 0x08 */
32 u32 w_err_upper_addr; /* 0x14 */
33 u32 w_pad_2; /* 0x10 */
34 u32 w_err_lower_addr; /* 0x1c */
35 u32 w_pad_3; /* 0x18 */
36 u32 w_control; /* 0x24 */
37 u32 w_pad_4; /* 0x20 */
[all …]
|
| D | xbow.h | 30 u32 link_ibf;
31 u32 filler0; /* filler for proper alignment */
32 u32 link_control;
33 u32 filler1;
34 u32 link_status;
35 u32 filler2;
36 u32 link_arb_upper;
37 u32 filler3;
38 u32 link_arb_lower;
39 u32 filler4;
[all …]
|
| /arch/mips/include/asm/pmc-sierra/msp71xx/ |
| D | msp_regops.h | 65 typedef unsigned int u32; typedef
71 static inline void set_value_reg32(volatile u32 *const addr, in set_value_reg32()
72 u32 const mask, in set_value_reg32()
73 u32 const value) in set_value_reg32()
75 u32 temp; in set_value_reg32()
94 static inline void set_reg32(volatile u32 *const addr, in set_reg32()
95 u32 const mask) in set_reg32()
97 u32 temp; in set_reg32()
115 static inline void clear_reg32(volatile u32 *const addr, in clear_reg32()
116 u32 const mask) in clear_reg32()
[all …]
|
| /arch/powerpc/kernel/ |
| D | sys_ppc32.c | 56 asmlinkage long ppc32_select(u32 n, compat_ulong_t __user *inp, in ppc32_select()
69 asmlinkage long compat_sys_sysfs(u32 option, u32 arg1, u32 arg2) in compat_sys_sysfs()
75 long compat_sys_ipc(u32 call, u32 first, u32 second, u32 third, compat_uptr_t ptr, in compat_sys_ipc()
76 u32 fifth) in compat_sys_ipc()
146 asmlinkage long compat_sys_sendfile(u32 out_fd, u32 in_fd, compat_off_t __user * offset, u32 count) in compat_sys_sendfile()
217 asmlinkage long compat_sys_prctl(u32 option, u32 arg2, u32 arg3, u32 arg4, u32 arg5) in compat_sys_prctl()
231 asmlinkage long compat_sys_sched_rr_get_interval(u32 pid, struct compat_timespec __user *interval) in compat_sys_sched_rr_get_interval()
251 asmlinkage long compat_sys_access(const char __user * filename, u32 mode) in compat_sys_access()
262 asmlinkage long compat_sys_creat(const char __user * pathname, u32 mode) in compat_sys_creat()
273 asmlinkage long compat_sys_waitpid(u32 pid, unsigned int __user * stat_addr, u32 options) in compat_sys_waitpid()
[all …]
|
| /arch/powerpc/platforms/iseries/ |
| D | processor_vpd.h | 36 u32 xHwNodeId; // Hardware node id x08-x0B
37 u32 xHwProcId; // Hardware processor id x0C-x0F
39 u32 xTypeNum; // Card Type/CCIN number x10-x13
40 u32 xModelNum; // Model/Feature number x14-x17
45 u32 xProcFreq; // Processor Frequency x30-x33
46 u32 xTimeBaseFreq; // Time Base Frequency x34-x37
48 u32 xChipEcLevel; // Chip EC Levels x38-x3B
49 u32 xProcIdReg; // PIR SPR value x3C-x3F
50 u32 xPVR; // PVR value x40-x43
53 u32 xInstCacheSize; // Instruction cache size in KB x50-x53
[all …]
|
| /arch/arm/mach-pxa/include/mach/ |
| D | ssp.h | 55 u32 cr0;
56 u32 cr1;
57 u32 to;
58 u32 psp;
63 u32 port;
64 u32 mode;
65 u32 flags;
66 u32 psp_flags;
67 u32 speed;
71 int ssp_write_word(struct ssp_dev *dev, u32 data);
[all …]
|
| /arch/powerpc/platforms/cell/ |
| D | pmu.c | 45 u32 _x = (x); \
65 (val) = (u32)(in_be64(&pmd_regs->reg) >> 32); \
73 u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr) in cbe_read_phys_ctr()
75 u32 val_in_latch, val = 0; in cbe_read_phys_ctr()
92 void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val) in cbe_write_phys_ctr()
95 u32 pm_ctrl; in cbe_write_phys_ctr()
125 u32 cbe_read_ctr(u32 cpu, u32 ctr) in cbe_read_ctr()
127 u32 val; in cbe_read_ctr()
128 u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1); in cbe_read_ctr()
139 void cbe_write_ctr(u32 cpu, u32 ctr, u32 val) in cbe_write_ctr()
[all …]
|