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Searched refs:v4 (Results 1 – 18 of 18) sorted by relevance

/arch/arm/mm/
Dproc-arm720.S86 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
112 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
127 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
155 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
Dproc-sa110.S168 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
169 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
171 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
176 mrc p15, 0, r0, c1, c0 @ get control register v4
Dproc-sa1100.S181 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
182 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
184 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
188 mrc p15, 0, r0, c1, c0 @ get control register v4
Dproc-arm920.S366 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
367 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
369 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
373 mrc p15, 0, r0, c1, c0 @ get control register v4
Dproc-arm922.S370 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
371 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
373 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
377 mrc p15, 0, r0, c1, c0 @ get control register v4
Dproc-arm1022.S381 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
382 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
384 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
388 mrc p15, 0, r0, c1, c0 @ get control register v4
Dproc-arm1020e.S399 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
400 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
402 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
406 mrc p15, 0, r0, c1, c0 @ get control register v4
Dproc-arm1026.S371 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
372 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
374 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
383 mrc p15, 0, r0, c1, c0 @ get control register v4
DMakefile30 obj-$(CONFIG_CPU_CACHE_V4) += cache-v4.o
46 obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o
Dproc-arm1020.S417 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
418 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
420 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
425 mrc p15, 0, r0, c1, c0 @ get control register v4
Dproc-arm926.S376 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
377 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
379 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
390 mrc p15, 0, r0, c1, c0 @ get control register v4
Dproc-arm925.S424 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
425 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
427 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
437 mrc p15, 0, r0, c1, c0 @ get control register v4
Dproc-feroceon.S468 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
469 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
471 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
476 mrc p15, 0, r0, c1, c0 @ get control register v4
/arch/arm/boot/compressed/
Dhead-shark.S57 mcr p15, 0, r0, c7, c7 @ flush I,D caches on v4
58 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
59 mcr p15, 0, r0, c8, c7 @ flush I,D TLBs on v4
Dhead.S714 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
715 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
/arch/s390/include/asm/
Detr.h67 unsigned int v4 : 1; /* validity bit ETR data frame 4 */ member
/arch/arm/include/asm/
Dcacheflush.h40 # define _CACHE v4
Dtlbflush.h85 # define _TLB v4