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Searched refs:OUT_RING (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/r128/
Dr128_state.c50 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3)); in r128_emit_clip_rects()
51 OUT_RING(boxes[0].x1); in r128_emit_clip_rects()
52 OUT_RING(boxes[0].x2 - 1); in r128_emit_clip_rects()
53 OUT_RING(boxes[0].y1); in r128_emit_clip_rects()
54 OUT_RING(boxes[0].y2 - 1); in r128_emit_clip_rects()
59 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3)); in r128_emit_clip_rects()
60 OUT_RING(boxes[1].x1); in r128_emit_clip_rects()
61 OUT_RING(boxes[1].x2 - 1); in r128_emit_clip_rects()
62 OUT_RING(boxes[1].y1); in r128_emit_clip_rects()
63 OUT_RING(boxes[1].y2 - 1); in r128_emit_clip_rects()
[all …]
Dr128_drv.h454 OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \
455 OUT_RING( R128_EVENT_CRTC_OFFSET ); \
517 #define OUT_RING( x ) do { \ macro
/drivers/gpu/drm/i830/
Di830_dma.c499 OUT_RING(tmp); in i830EmitContextVerified()
506 OUT_RING(STATE3D_CONST_BLEND_COLOR_CMD); in i830EmitContextVerified()
507 OUT_RING(code[I830_CTXREG_BLENDCOLR]); in i830EmitContextVerified()
514 OUT_RING(tmp); in i830EmitContextVerified()
521 OUT_RING(STATE3D_MAP_COORD_SETBIND_CMD); in i830EmitContextVerified()
522 OUT_RING(code[I830_CTXREG_MCSB1]); in i830EmitContextVerified()
526 OUT_RING(0); in i830EmitContextVerified()
544 OUT_RING(code[I830_TEXREG_MI0]); /* TM0LI */ in i830EmitTexVerified()
545 OUT_RING(code[I830_TEXREG_MI1]); /* TM0S0 */ in i830EmitTexVerified()
546 OUT_RING(code[I830_TEXREG_MI2]); /* TM0S1 */ in i830EmitTexVerified()
[all …]
Di830_irq.c66 OUT_RING(0); in i830_emit_irq()
67 OUT_RING(GFX_OP_USER_INTERRUPT); in i830_emit_irq()
Di830_drv.h168 #define OUT_RING(n) do { \ macro
/drivers/gpu/drm/radeon/
Dradeon_state.c435 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); in radeon_emit_clip_rect()
436 OUT_RING((box->y1 << 16) | box->x1); in radeon_emit_clip_rect()
437 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); in radeon_emit_clip_rect()
438 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1)); in radeon_emit_clip_rect()
467 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6)); in radeon_emit_state()
468 OUT_RING(ctx->pp_misc); in radeon_emit_state()
469 OUT_RING(ctx->pp_fog_color); in radeon_emit_state()
470 OUT_RING(ctx->re_solid_color); in radeon_emit_state()
471 OUT_RING(ctx->rb3d_blendcntl); in radeon_emit_state()
472 OUT_RING(ctx->rb3d_depthoffset); in radeon_emit_state()
[all …]
Dr300_cmdbuf.c71 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); in r300_emit_cliprects()
103 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) | in r300_emit_cliprects()
105 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) | in r300_emit_cliprects()
117 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1)); in r300_emit_cliprects()
118 OUT_RING(0); in r300_emit_cliprects()
119 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK); in r300_emit_cliprects()
144 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r300_emit_cliprects()
145 OUT_RING(R300_RB3D_DC_FLUSH); in r300_emit_cliprects()
148 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); in r300_emit_cliprects()
149 OUT_RING(RADEON_WAIT_3D_IDLECLEAN); in r300_emit_cliprects()
[all …]
Dradeon_drv.h1266 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1267 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1272 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1273 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1278 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1279 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1285 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1286 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1291 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1292 OUT_RING(RADEON_RB3D_DC_FLUSH); \
[all …]
Dradeon_cp.c450 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); in radeon_do_cp_start()
451 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | in radeon_do_cp_start()
/drivers/gpu/drm/i810/
Di810_dma.c476 OUT_RING(GFX_OP_COLOR_FACTOR); in i810EmitContextVerified()
477 OUT_RING(code[I810_CTXREG_CF1]); in i810EmitContextVerified()
479 OUT_RING(GFX_OP_STIPPLE); in i810EmitContextVerified()
480 OUT_RING(code[I810_CTXREG_ST1]); in i810EmitContextVerified()
487 OUT_RING(tmp); in i810EmitContextVerified()
494 OUT_RING(0); in i810EmitContextVerified()
508 OUT_RING(GFX_OP_MAP_INFO); in i810EmitTexVerified()
509 OUT_RING(code[I810_TEXREG_MI1]); in i810EmitTexVerified()
510 OUT_RING(code[I810_TEXREG_MI2]); in i810EmitTexVerified()
511 OUT_RING(code[I810_TEXREG_MI3]); in i810EmitTexVerified()
[all …]
Di810_drv.h163 #define OUT_RING(n) do { \ macro
/drivers/gpu/drm/i915/
Di915_dma.c379 OUT_RING(cmd); in i915_emit_cmds()
386 OUT_RING(cmd); in i915_emit_cmds()
391 OUT_RING(0); in i915_emit_cmds()
419 OUT_RING(GFX_OP_DRAWRECT_INFO_I965); in i915_emit_box()
420 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); in i915_emit_box()
421 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); in i915_emit_box()
422 OUT_RING(DR4); in i915_emit_box()
426 OUT_RING(GFX_OP_DRAWRECT_INFO); in i915_emit_box()
427 OUT_RING(DR1); in i915_emit_box()
428 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); in i915_emit_box()
[all …]
Di915_irq.c314 OUT_RING(MI_STORE_DWORD_INDEX); in i915_emit_irq()
315 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); in i915_emit_irq()
316 OUT_RING(dev_priv->counter); in i915_emit_irq()
317 OUT_RING(MI_USER_INTERRUPT); in i915_emit_irq()
Di915_gem.c925 OUT_RING(MI_STORE_DWORD_INDEX); in i915_add_request()
926 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); in i915_add_request()
927 OUT_RING(seqno); in i915_add_request()
929 OUT_RING(MI_USER_INTERRUPT); in i915_add_request()
981 OUT_RING(cmd); in i915_retire_commands()
982 OUT_RING(0); /* noop */ in i915_retire_commands()
1203 OUT_RING(cmd); in i915_gem_flush()
1204 OUT_RING(0); /* noop */ in i915_gem_flush()
2459 OUT_RING(MI_BATCH_BUFFER); in i915_dispatch_gem_execbuffer()
2460 OUT_RING(exec_start | MI_BATCH_NON_SECURE); in i915_dispatch_gem_execbuffer()
[all …]
Di915_drv.h719 #define OUT_RING(n) do { \ macro
/drivers/video/intelfb/
Dintelfbhw.c1536 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE); in do_flush()
1537 OUT_RING(MI_NOOP); in do_flush()
1674 OUT_RING(br00); in intelfbhw_do_fillrect()
1675 OUT_RING(br13); in intelfbhw_do_fillrect()
1676 OUT_RING(br14); in intelfbhw_do_fillrect()
1677 OUT_RING(br09); in intelfbhw_do_fillrect()
1678 OUT_RING(br16); in intelfbhw_do_fillrect()
1679 OUT_RING(MI_NOOP); in intelfbhw_do_fillrect()
1723 OUT_RING(br00); in intelfbhw_do_bitblt()
1724 OUT_RING(br13); in intelfbhw_do_bitblt()
[all …]
Dintelfbhw.h534 #define OUT_RING(n) do { \ macro