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Searched refs:ia64_setreg (Results 1 – 13 of 13) sorted by relevance

/arch/ia64/include/asm/
Dprocessor.h441 case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break; \
442 case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break; \
443 case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break; \
444 case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break; \
445 case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break; \
446 case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break; \
447 case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break; \
448 case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break; \
538 ia64_setreg(_IA64_REG_PSR_L, psr); in ia64_set_psr()
551 ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2)); in ia64_itr()
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Ddelay.h25 ia64_setreg(_IA64_REG_CR_ITM, val); in ia64_set_itm()
42 ia64_setreg(_IA64_REG_CR_ITV, val); in ia64_set_itv()
55 ia64_setreg(_IA64_REG_AR_ITC, val); in ia64_set_itc()
Dintrinsics.h230 #define ia64_setreg IA64_INTRINSIC_API(setreg) macro
/arch/ia64/ia32/
Dia32_support.c123 ia64_setreg(_IA64_REG_AR_EFLAG, eflag); in ia32_load_state()
124 ia64_setreg(_IA64_REG_AR_FSR, fsr); in ia32_load_state()
125 ia64_setreg(_IA64_REG_AR_FCR, fcr); in ia32_load_state()
126 ia64_setreg(_IA64_REG_AR_FIR, fir); in ia32_load_state()
127 ia64_setreg(_IA64_REG_AR_FDR, fdr); in ia32_load_state()
235 ia64_setreg(_IA64_REG_AR_CFLAG, (((ulong) IA32_CR4 << 32) | IA32_CR0)); in ia32_cpu_init()
Dia32_signal.c231 ia64_setreg(_IA64_REG_AR_FSR, new_fsr); in save_ia32_fpstate_live()
373 ia64_setreg(_IA64_REG_AR_FSR, fsr); in restore_ia32_fpstate_live()
374 ia64_setreg(_IA64_REG_AR_FCR, fcr); in restore_ia32_fpstate_live()
375 ia64_setreg(_IA64_REG_AR_FIR, fir); in restore_ia32_fpstate_live()
376 ia64_setreg(_IA64_REG_AR_FDR, fdr); in restore_ia32_fpstate_live()
720 ia64_setreg(_IA64_REG_AR_EFLAG, flag); in restore_sigcontext_ia32()
/arch/ia64/kernel/
Dmachine_kexec.c99 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); in ia64_machine_kexec()
100 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); in ia64_machine_kexec()
112 ia64_setreg(_IA64_REG_CR_TPR, 0); in ia64_machine_kexec()
Dirq_ia64.c504 ia64_setreg(_IA64_REG_CR_TPR, vector); in ia64_handle_irq()
519 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr); in ia64_handle_irq()
563 ia64_setreg(_IA64_REG_CR_TPR, vector); in ia64_process_pending_intr()
587 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr); in ia64_process_pending_intr()
Dsetup.c1015 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR in cpu_init()
1036 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); in cpu_init()
1037 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); in cpu_init()
1040 ia64_setreg(_IA64_REG_CR_TPR, 0); in cpu_init()
Dmca.c640 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); in ia64_mca_cmc_vector_setup()
669 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); in ia64_mca_cmc_vector_disable()
695 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); in ia64_mca_cmc_vector_enable()
Dperfmon.c715 ia64_setreg(_IA64_REG_PSR_L, val); in pfm_set_psr_l()
1042 ia64_setreg(_IA64_REG_CR_DCR, ia64_getreg(_IA64_REG_CR_DCR) & ~IA64_DCR_PP); in pfm_restore_monitoring()
1099 ia64_setreg(_IA64_REG_CR_DCR, ia64_getreg(_IA64_REG_CR_DCR) | IA64_DCR_PP); in pfm_restore_monitoring()
4020 ia64_setreg(_IA64_REG_CR_DCR, ia64_getreg(_IA64_REG_CR_DCR) & ~IA64_DCR_PP); in pfm_stop()
4114 ia64_setreg(_IA64_REG_CR_DCR, ia64_getreg(_IA64_REG_CR_DCR) | IA64_DCR_PP); in pfm_start()
5815 ia64_setreg(_IA64_REG_CR_DCR, dcr & ~IA64_DCR_PP); in pfm_syst_wide_update_task()
5827 ia64_setreg(_IA64_REG_CR_DCR, dcr |IA64_DCR_PP); in pfm_syst_wide_update_task()
6733 ia64_setreg(_IA64_REG_CR_PMV, IA64_PERFMON_VECTOR); in pfm_init_percpu()
/arch/ia64/hp/sim/boot/
Dbootloader.c164 ia64_setreg(_IA64_REG_AR_KR0, 0xffffc000000UL); in start_bootloader()
/arch/ia64/kvm/
Dvcpu.c317 ia64_setreg(_IA64_REG_AR_RSC, new_rsc); in get_rse_reg()
338 ia64_setreg(_IA64_REG_AR_RSC, old_rsc); in get_rse_reg()
361 ia64_setreg(_IA64_REG_AR_RSC, new_rsc); in set_rse_reg()
384 ia64_setreg(_IA64_REG_AR_RNAT, rnat); in set_rse_reg()
393 ia64_setreg(_IA64_REG_AR_BSPSTORE, bspstore); in set_rse_reg()
394 ia64_setreg(_IA64_REG_AR_RNAT, rnat); in set_rse_reg()
397 ia64_setreg(_IA64_REG_AR_RSC, old_rsc); in set_rse_reg()
Dvcpu.h526 ia64_setreg(_IA64_REG_CR_DCR, val); in vcpu_set_dcr()