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/drivers/net/chelsio/
Dregs.h46 #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE) argument
50 #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE) argument
54 #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE) argument
58 #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE) argument
62 #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE) argument
66 #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE) argument
71 #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY) argument
72 #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY) argument
75 #define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS) argument
79 #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS) argument
[all …]
Dfpga_defs.h55 #define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV) argument
56 #define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV) argument
60 #define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT) argument
61 #define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT) argument
66 #define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL) argument
70 #define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE) argument
74 #define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE) argument
78 #define V_MI0_BUSY(x) ((x) << S_MI0_BUSY) argument
82 #define V_MI0_MDIO(x) ((x) << S_MI0_MDIO) argument
89 #define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR) argument
[all …]
Delmer0.h59 #define V_MI1_MDI_ENABLE(x) ((x) << S_MI1_MDI_ENABLE) argument
63 #define V_MI1_MDI_INVERT(x) ((x) << S_MI1_MDI_INVERT) argument
67 #define V_MI1_PREAMBLE_ENABLE(x) ((x) << S_MI1_PREAMBLE_ENABLE) argument
72 #define V_MI1_SOF(x) ((x) << S_MI1_SOF) argument
73 #define G_MI1_SOF(x) (((x) >> S_MI1_SOF) & M_MI1_SOF) argument
77 #define V_MI1_CLK_DIV(x) ((x) << S_MI1_CLK_DIV) argument
78 #define G_MI1_CLK_DIV(x) (((x) >> S_MI1_CLK_DIV) & M_MI1_CLK_DIV) argument
84 #define V_MI1_REG_ADDR(x) ((x) << S_MI1_REG_ADDR) argument
85 #define G_MI1_REG_ADDR(x) (((x) >> S_MI1_REG_ADDR) & M_MI1_REG_ADDR) argument
89 #define V_MI1_PHY_ADDR(x) ((x) << S_MI1_PHY_ADDR) argument
[all …]
/drivers/staging/epl/
DBenchmark.h88 #define BENCHMARK_SET(x) MCF_GPIO_PODR_PCIBG |= (1 << (x)) // (x+1) argument
89 #define BENCHMARK_RESET(x) MCF_GPIO_PODR_PCIBG &= ~(1 << (x)) // (x+1) argument
90 #define BENCHMARK_TOGGLE(x) MCF_GPIO_PODR_PCIBR ^= (1 << (x - 5)) argument
152 #define BENCHMARK_MOD_01_SET(x) BENCHMARK_SET(x) argument
153 #define BENCHMARK_MOD_01_RESET(x) BENCHMARK_RESET(x) argument
154 #define BENCHMARK_MOD_01_TOGGLE(x) BENCHMARK_TOGGLE(x) argument
156 #define BENCHMARK_MOD_01_SET(x) argument
157 #define BENCHMARK_MOD_01_RESET(x) argument
158 #define BENCHMARK_MOD_01_TOGGLE(x) argument
162 #define BENCHMARK_MOD_02_SET(x) BENCHMARK_SET(x) argument
[all …]
DEdrvFec5282.h200 #define FEC_MMFR_DATA(x) (((x) & 0xFFFF)) argument
202 #define FEC_MMFR_RA(x) (((x) & 0x1F) << 18) argument
203 #define FEC_MMFR_PA(x) (((x) & 0x1F) << 23) argument
208 #define FEC_MSCR_MII_SPEED(x) (((x) & 0x1F) << 1) argument
220 #define FEC_RCR_MAX_FL(x) (((x) & 0x07FF) << 16) argument
228 #define FEC_PALR_BYTE3(x) (((x) & 0xFF) << 0) argument
229 #define FEC_PALR_BYTE2(x) (((x) & 0xFF) << 8) argument
230 #define FEC_PALR_BYTE1(x) (((x) & 0xFF) << 16) argument
231 #define FEC_PALR_BYTE0(x) (((x) & 0xFF) << 24) argument
234 #define FEC_PAUR_BYTE5(x) (((x) & 0xFF) << 16) argument
[all …]
/drivers/net/cxgb3/
Dregs.h4 #define V_CONGMODE(x) ((x) << S_CONGMODE) argument
8 #define V_TNLFLMODE(x) ((x) << S_TNLFLMODE) argument
12 #define V_FATLPERREN(x) ((x) << S_FATLPERREN) argument
16 #define V_DROPPKT(x) ((x) << S_DROPPKT) argument
20 #define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL) argument
25 #define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE) argument
29 #define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE) argument
32 #define V_FLMODE(x) ((x) << S_FLMODE) argument
37 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT) argument
40 #define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ) argument
[all …]
Dsge_defs.h10 #define V_EC_CREDITS(x) ((x) << S_EC_CREDITS) argument
11 #define G_EC_CREDITS(x) (((x) >> S_EC_CREDITS) & M_EC_CREDITS) argument
14 #define V_EC_GTS(x) ((x) << S_EC_GTS) argument
19 #define V_EC_INDEX(x) ((x) << S_EC_INDEX) argument
20 #define G_EC_INDEX(x) (((x) >> S_EC_INDEX) & M_EC_INDEX) argument
24 #define V_EC_SIZE(x) ((x) << S_EC_SIZE) argument
25 #define G_EC_SIZE(x) (((x) >> S_EC_SIZE) & M_EC_SIZE) argument
29 #define V_EC_BASE_LO(x) ((x) << S_EC_BASE_LO) argument
30 #define G_EC_BASE_LO(x) (((x) >> S_EC_BASE_LO) & M_EC_BASE_LO) argument
34 #define V_EC_BASE_HI(x) ((x) << S_EC_BASE_HI) argument
[all …]
Dt3_cpl.h190 #define V_OPCODE(x) ((x) << S_OPCODE) argument
191 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF) argument
192 #define G_TID(x) ((x) & 0xFFFFFF) argument
195 #define G_QNUM(x) (((x) >> S_QNUM) & 0xFFFF) argument
199 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) argument
247 #define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS) argument
248 #define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS) argument
252 #define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT) argument
253 #define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT) argument
257 #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT) argument
[all …]
/drivers/infiniband/hw/cxgb3/
Dtcb.h38 #define V_TCB_T_STATE(x) ((x) << S_TCB_T_STATE) argument
43 #define V_TCB_TIMER(x) ((x) << S_TCB_TIMER) argument
48 #define V_TCB_DACK_TIMER(x) ((x) << S_TCB_DACK_TIMER) argument
53 #define V_TCB_DEL_FLAG(x) ((x) << S_TCB_DEL_FLAG) argument
58 #define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX) argument
63 #define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL) argument
68 #define V_TCB_TOS(x) ((x) << S_TCB_TOS) argument
73 #define V_TCB_MAX_RT(x) ((x) << S_TCB_MAX_RT) argument
78 #define V_TCB_T_RXTSHIFT(x) ((x) << S_TCB_T_RXTSHIFT) argument
83 #define V_TCB_T_DUPACKS(x) ((x) << S_TCB_T_DUPACKS) argument
[all …]
Dcxio_wr.h59 #define SEQ32_GE(x,y) (!( (((u32) (x)) - ((u32) (y))) & 0x80000000 )) argument
139 #define V_FW_RIWR_OP(x) ((x) << S_FW_RIWR_OP) argument
140 #define G_FW_RIWR_OP(x) ((((x) >> S_FW_RIWR_OP)) & M_FW_RIWR_OP) argument
144 #define V_FW_RIWR_SOPEOP(x) ((x) << S_FW_RIWR_SOPEOP) argument
148 #define V_FW_RIWR_FLAGS(x) ((x) << S_FW_RIWR_FLAGS) argument
149 #define G_FW_RIWR_FLAGS(x) ((((x) >> S_FW_RIWR_FLAGS)) & M_FW_RIWR_FLAGS) argument
152 #define V_FW_RIWR_TID(x) ((x) << S_FW_RIWR_TID) argument
155 #define V_FW_RIWR_LEN(x) ((x) << S_FW_RIWR_LEN) argument
158 #define V_FW_RIWR_GEN(x) ((x) << S_FW_RIWR_GEN) argument
204 #define V_FR_PAGE_COUNT(x) ((x) << S_FR_PAGE_COUNT) argument
[all …]
/drivers/atm/
Dhe.h55 #define TPDRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TPDRQ_SIZE<<3)-1)) argument
59 #define RBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_RBRQ_SIZE<<3)-1)) argument
63 #define TBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TBRQ_SIZE<<2)-1)) argument
68 #define RBPL_MASK(x) (((unsigned long)(x))&((CONFIG_RBPL_SIZE<<3)-1)) argument
73 #define RBPS_MASK(x) (((unsigned long)(x))&((CONFIG_RBPS_SIZE<<3)-1)) argument
114 #define ITYPE_GROUP(x) (x & 0x7) argument
115 #define ITYPE_TYPE(x) (x & 0xf8) argument
149 #define TPD_ADDR(x) ((x) & TPD_MASK) argument
150 #define TPD_INDEX(x) (TPD_ADDR(x) >> TPD_ADDR_SHIFT) argument
220 #define RBP_INDEX(x) (((long)(x) >> RBP_INDEX_OFF) & 0xffff) argument
[all …]
/drivers/video/mbx/
Dreg_bits.h32 #define Core_Pll_M(x) ((x) << FShft(CORE_PLL_M)) argument
34 #define Core_Pll_N(x) ((x) << FShft(CORE_PLL_N)) argument
36 #define Core_Pll_P(x) ((x) << FShft(CORE_PLL_P)) argument
41 #define Disp_Pll_M(x) ((x) << FShft(DISP_PLL_M)) argument
43 #define Disp_Pll_N(x) ((x) << FShft(DISP_PLL_N)) argument
45 #define Disp_Pll_P(x) ((x) << FShft(DISP_PLL_P)) argument
87 #define Pixclkdiv_Pd(x) ((x) << FShft(PIXCLKDIV_PD)) argument
91 #define Lcdcfg_In_Fmt(x) ((x) << FShft(LCDCFG_IN_FMT)) argument
167 #define Lmtim_Tras(x) ((x) << FShft(LMTIM_TRAS)) argument
169 #define Lmtim_Trp(x) ((x) << FShft(LMTIM_TRP)) argument
[all …]
/drivers/macintosh/
Dtherm_windtunnel.c81 } x; variable
83 #define T(x,y) (((x)<<8) | (y)*0x100/10 ) argument
113 return sprintf(buf, "%d.%d\n", x.temp>>8, (x.temp & 255)*10/256 ); in show_cpu_temperature()
119 return sprintf(buf, "%d.%d\n", x.casetemp>>8, (x.casetemp & 255)*10/256 ); in show_case_temperature()
170 write_reg( x.fan, 0x25, val, 1 ); in tune_fan()
171 write_reg( x.fan, 0x20, 0, 1 ); in tune_fan()
172 print_temp("CPU-temp: ", x.temp ); in tune_fan()
173 if( x.casetemp ) in tune_fan()
174 print_temp(", Case: ", x.casetemp ); in tune_fan()
175 printk(", Fan: %d (tuned %+d)\n", 11-fan_setting, x.fan_level-fan_setting ); in tune_fan()
[all …]
/drivers/staging/rt2870/common/
Deeprom.c52 IN UINT32 *x) in RaiseClock() argument
54 *x = *x | EESK; in RaiseClock()
55 RTMP_IO_WRITE32(pAd, E2PROM_CSR, *x); in RaiseClock()
62 IN UINT32 *x) in LowerClock() argument
64 *x = *x & ~EESK; in LowerClock()
65 RTMP_IO_WRITE32(pAd, E2PROM_CSR, *x); in LowerClock()
73 UINT32 x,i; in ShiftInBits() local
76 RTMP_IO_READ32(pAd, E2PROM_CSR, &x); in ShiftInBits()
78 x &= ~( EEDO | EEDI); in ShiftInBits()
83 RaiseClock(pAd, &x); in ShiftInBits()
[all …]
/drivers/staging/rt2860/common/
Deeprom.c42 IN UINT32 *x) in RaiseClock() argument
44 *x = *x | EESK; in RaiseClock()
45 RTMP_IO_WRITE32(pAd, E2PROM_CSR, *x); in RaiseClock()
52 IN UINT32 *x) in LowerClock() argument
54 *x = *x & ~EESK; in LowerClock()
55 RTMP_IO_WRITE32(pAd, E2PROM_CSR, *x); in LowerClock()
63 UINT32 x,i; in ShiftInBits() local
66 RTMP_IO_READ32(pAd, E2PROM_CSR, &x); in ShiftInBits()
68 x &= ~( EEDO | EEDI); in ShiftInBits()
73 RaiseClock(pAd, &x); in ShiftInBits()
[all …]
/drivers/staging/echo/
Dbit_operations.h130 static __inline__ uint8_t bit_reverse8(uint8_t x) in bit_reverse8() argument
134 return ((x * 0x0802U & 0x22110U) | (x * 0x8020U & 0x88440U)) * in bit_reverse8()
138 x = (x >> 4) | (x << 4); in bit_reverse8()
139 x = ((x & 0xCC) >> 2) | ((x & 0x33) << 2); in bit_reverse8()
140 return ((x & 0xAA) >> 1) | ((x & 0x55) << 1); in bit_reverse8()
162 int one_bits32(uint32_t x);
167 uint32_t make_mask32(uint32_t x);
172 uint16_t make_mask16(uint16_t x);
178 static __inline__ uint32_t least_significant_one32(uint32_t x) in least_significant_one32() argument
180 return (x & (-(int32_t) x)); in least_significant_one32()
[all …]
/drivers/usb/c67x00/
Dc67x00.h43 #define USB_CTL_REG(x) ((x) ? 0xC0AA : 0xC08A) argument
45 #define LOW_SPEED_PORT(x) ((x) ? 0x0800 : 0x0400) argument
47 #define PORT_RES_EN(x) ((x) ? 0x0100 : 0x0080) argument
48 #define SOF_EOP_EN(x) ((x) ? 0x0002 : 0x0001) argument
51 #define USB_STAT_REG(x) ((x) ? 0xC0B0 : 0xC090) argument
70 #define HOST_CTL_REG(x) ((x) ? 0xC0A0 : 0xC080) argument
78 #define HOST_IRQ_EN_REG(x) ((x) ? 0xC0AC : 0xC08C) argument
88 #define PORT_CONNECT_CHANGE(x) ((x) ? 0x0020 : 0x0010) argument
89 #define PORT_SE0_STATUS(x) ((x) ? 0x0008 : 0x0004) argument
92 #define HOST_FRAME_REG(x) ((x) ? 0xC0B6 : 0xC096) argument
[all …]
/drivers/video/via/
Dhw.h30 #define IGA1_HOR_TOTAL_FORMULA(x) (((x)/8)-5) argument
31 #define IGA1_HOR_ADDR_FORMULA(x) (((x)/8)-1) argument
32 #define IGA1_HOR_BLANK_START_FORMULA(x) (((x)/8)-1) argument
33 #define IGA1_HOR_BLANK_END_FORMULA(x, y) (((x+y)/8)-1) argument
34 #define IGA1_HOR_SYNC_START_FORMULA(x) ((x)/8) argument
35 #define IGA1_HOR_SYNC_END_FORMULA(x, y) ((x+y)/8) argument
37 #define IGA1_VER_TOTAL_FORMULA(x) ((x)-2) argument
38 #define IGA1_VER_ADDR_FORMULA(x) ((x)-1) argument
39 #define IGA1_VER_BLANK_START_FORMULA(x) ((x)-1) argument
40 #define IGA1_VER_BLANK_END_FORMULA(x, y) ((x+y)-1) argument
[all …]
/drivers/scsi/qla2xxx/
Dqla_dbg.h35 #define DEBUG(x) do { if (ql2xextended_error_logging) { x; } } while (0) argument
38 #define DEBUG1(x) do {x;} while (0) argument
40 #define DEBUG1(x) do {} while (0) argument
43 #define DEBUG2(x) do { if (ql2xextended_error_logging) { x; } } while (0) argument
44 #define DEBUG2_3(x) do { if (ql2xextended_error_logging) { x; } } while (0) argument
45 #define DEBUG2_3_11(x) do { if (ql2xextended_error_logging) { x; } } while (0) argument
46 #define DEBUG2_9_10(x) do { if (ql2xextended_error_logging) { x; } } while (0) argument
47 #define DEBUG2_11(x) do { if (ql2xextended_error_logging) { x; } } while (0) argument
48 #define DEBUG2_13(x) do { if (ql2xextended_error_logging) { x; } } while (0) argument
49 #define DEBUG2_16(x) do { if (ql2xextended_error_logging) { x; } } while (0) argument
[all …]
/drivers/scsi/
Dppa.h122 #define IN_EPP_MODE(x) (x == PPA_EPP_8 || x == PPA_EPP_16 || x == PPA_EPP_32) argument
128 #define r_dtr(x) (unsigned char)inb((x)) argument
129 #define r_str(x) (unsigned char)inb((x)+1) argument
130 #define r_ctr(x) (unsigned char)inb((x)+2) argument
131 #define r_epp(x) (unsigned char)inb((x)+4) argument
132 #define r_fifo(x) (unsigned char)inb((x)) /* x must be base_hi */ argument
134 #define r_ecr(x) (unsigned char)inb((x)+0x2) /* x must be base_hi */ argument
136 #define w_dtr(x,y) outb(y, (x)) argument
137 #define w_str(x,y) outb(y, (x)+1) argument
138 #define w_epp(x,y) outb(y, (x)+4) argument
[all …]
Dimm.h115 #define IN_EPP_MODE(x) (x == IMM_EPP_8 || x == IMM_EPP_16 || x == IMM_EPP_32) argument
121 #define r_dtr(x) (unsigned char)inb((x)) argument
122 #define r_str(x) (unsigned char)inb((x)+1) argument
123 #define r_ctr(x) (unsigned char)inb((x)+2) argument
124 #define r_epp(x) (unsigned char)inb((x)+4) argument
125 #define r_fifo(x) (unsigned char)inb((x)) /* x must be base_hi */ argument
127 #define r_ecr(x) (unsigned char)inb((x)+2) /* x must be base_hi */ argument
129 #define w_dtr(x,y) outb(y, (x)) argument
130 #define w_str(x,y) outb(y, (x)+1) argument
131 #define w_epp(x,y) outb(y, (x)+4) argument
[all …]
/drivers/pcmcia/
Dvrc4173_cardu.h134 #define IO_WIN_EN(x) (0x40 << (x)) argument
135 #define MEM_WIN_EN(x) (0x01 << (x)) argument
138 #define IO_WIN_CNT_MASK(x) (0x03 << ((x) << 2)) argument
139 #define IO_WIN_DATA_AUTOSZ(x) (0x02 << ((x) << 2)) argument
140 #define IO_WIN_DATA_16BIT(x) (0x01 << ((x) << 2)) argument
142 #define IO_WIN_SA(x) (0x008 + ((x) << 2)) argument
143 #define IO_WIN_EA(x) (0x00a + ((x) << 2)) argument
145 #define MEM_WIN_SA(x) (0x010 + ((x) << 3)) argument
148 #define MEM_WIN_EA(x) (0x012 + ((x) << 3)) argument
150 #define MEM_WIN_OA(x) (0x014 + ((x) << 3)) argument
[all …]
/drivers/net/
Dtehuti.h77 #define MIN(x, y) ((x) < (y) ? (x) : (y)) argument
80 # define H32_64(x) (u32) ((u64)(x) >> 32) argument
81 # define L32_64(x) (u32) ((u64)(x) & 0xffffffff) argument
83 # define H32_64(x) 0 argument
84 # define L32_64(x) ((u32) (x)) argument
90 # define CPU_CHIP_SWAP32(x) swab32(x) argument
91 # define CPU_CHIP_SWAP16(x) swab16(x) argument
93 # define CPU_CHIP_SWAP32(x) (x) argument
94 # define CPU_CHIP_SWAP16(x) (x) argument
136 #define GET_BITS_SHIFT(x, nbits, nshift) (((x)>>nshift)&BITS_MASK(nbits)) argument
[all …]
Dsmc911x.h710 #define IS_REV_A(x) ((x & 0xFFFF)==0) argument
719 #define SMC_SET_TX_FIFO(lp, x) SMC_outl( x, lp, TX_DATA_FIFO ) argument
730 #define SMC_SET_IRQ_CFG(lp, x) SMC_outl( x, lp, INT_CFG ) argument
732 #define SMC_ACK_INT(lp, x) SMC_outl( x, lp, INT_STS ) argument
734 #define SMC_SET_INT_EN(lp, x) SMC_outl( x, lp, INT_EN ) argument
736 #define SMC_SET_BYTE_TEST(lp, x) SMC_outl( x, lp, BYTE_TEST ) argument
738 #define SMC_SET_FIFO_INT(lp, x) SMC_outl( x, lp, FIFO_INT ) argument
739 #define SMC_SET_FIFO_TDA(lp, x) \ argument
745 SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 ); \
748 #define SMC_SET_FIFO_TSL(lp, x) \ argument
[all …]
/drivers/usb/host/
Disp1760-hcd.h57 #define ISP_BANK(x) ((x) << 16) argument
175 #define PTD_LENGTH(x) (((u32) x) << 3) argument
176 #define PTD_MAXPACKET(x) (((u32) x) << 18) argument
177 #define PTD_MULTI(x) (((u32) x) << 29) argument
178 #define PTD_ENDPOINT(x) (((u32) x) << 31) argument
180 #define PTD_DEVICE_ADDR(x) (((u32) x) << 3) argument
181 #define PTD_PID_TOKEN(x) (((u32) x) << 10) argument
186 #define PTD_PORT_NUM(x) (((u32) x) << 18) argument
187 #define PTD_HUB_NUM(x) (((u32) x) << 25) argument
188 #define PTD_PING(x) (((u32) x) << 26) argument
[all …]

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