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Searched refs:I915_READ (Results 1 – 25 of 31) sorted by relevance

12

/drivers/gpu/drm/i915/
Di915_ums.c48 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE); in i915_pipe_enabled()
70 array[i] = I915_READ(reg + (i << 2)); in i915_save_palette()
101 dev_priv->regfile.saveCURACNTR = I915_READ(_CURACNTR); in i915_save_display_reg()
102 dev_priv->regfile.saveCURAPOS = I915_READ(_CURAPOS); in i915_save_display_reg()
103 dev_priv->regfile.saveCURABASE = I915_READ(_CURABASE); in i915_save_display_reg()
104 dev_priv->regfile.saveCURBCNTR = I915_READ(_CURBCNTR); in i915_save_display_reg()
105 dev_priv->regfile.saveCURBPOS = I915_READ(_CURBPOS); in i915_save_display_reg()
106 dev_priv->regfile.saveCURBBASE = I915_READ(_CURBBASE); in i915_save_display_reg()
108 dev_priv->regfile.saveCURSIZE = I915_READ(CURSIZE); in i915_save_display_reg()
111 dev_priv->regfile.savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL); in i915_save_display_reg()
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Di915_suspend.c73 dev_priv->regfile.saveVGA0 = I915_READ(VGA0); in i915_save_vga()
74 dev_priv->regfile.saveVGA1 = I915_READ(VGA1); in i915_save_vga()
75 dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD); in i915_save_vga()
76 dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev)); in i915_save_vga()
198 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); in i915_save_display()
207 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL); in i915_save_display()
208 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1); in i915_save_display()
209 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2); in i915_save_display()
210 dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL); in i915_save_display()
211 dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2); in i915_save_display()
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Di915_irq.c119 u32 pipestat = I915_READ(reg) & 0x7fff0000; in i915_enable_pipestat()
134 u32 pipestat = I915_READ(reg) & 0x7fff0000; in i915_disable_pipestat()
187 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE; in i915_pipe_enabled()
215 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; in i915_get_vblank_counter()
216 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; in i915_get_vblank_counter()
217 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; in i915_get_vblank_counter()
236 return I915_READ(reg); in gm45_get_vblank_counter()
257 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff); in i915_get_crtc_scanoutpos()
263 position = I915_READ(PIPEDSL(pipe)); in i915_get_crtc_scanoutpos()
275 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; in i915_get_crtc_scanoutpos()
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Dintel_pm.c61 fbc_ctl = I915_READ(FBC_CONTROL); in i8xx_disable_fbc()
69 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { in i8xx_disable_fbc()
124 return I915_READ(FBC_CONTROL) & FBC_CTL_EN; in i8xx_fbc_enabled()
149 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); in g4x_enable_fbc()
160 dpfc_ctl = I915_READ(DPFC_CONTROL); in g4x_disable_fbc()
173 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; in g4x_fbc_enabled()
183 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); in sandybridge_blit_fbc_update()
208 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); in ironlake_enable_fbc()
240 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); in ironlake_disable_fbc()
253 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; in ironlake_fbc_enabled()
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Di915_debugfs.c434 I915_READ(VLV_IER)); in i915_interrupt_info()
436 I915_READ(VLV_IIR)); in i915_interrupt_info()
438 I915_READ(VLV_IIR_RW)); in i915_interrupt_info()
440 I915_READ(VLV_IMR)); in i915_interrupt_info()
444 I915_READ(PIPESTAT(pipe))); in i915_interrupt_info()
447 I915_READ(VLV_MASTER_IER)); in i915_interrupt_info()
450 I915_READ(GTIER)); in i915_interrupt_info()
452 I915_READ(GTIIR)); in i915_interrupt_info()
454 I915_READ(GTIMR)); in i915_interrupt_info()
457 I915_READ(GEN6_PMIER)); in i915_interrupt_info()
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Dintel_ddi.c151 if (I915_READ(reg) & DDI_BUF_IS_IDLE) in intel_wait_ddi_buf_idle()
230 temp = I915_READ(_FDI_RXA_MISC); in hsw_fdi_link_train()
238 temp = I915_READ(DP_TP_STATUS(PORT_E)); in hsw_fdi_link_train()
252 temp = I915_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
258 temp = I915_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
271 temp = I915_READ(_FDI_RXA_MISC); in hsw_fdi_link_train()
770 val = I915_READ(SPLL_CTL); in intel_ddi_put_crtc_pll()
780 val = I915_READ(WRPLL_CTL1); in intel_ddi_put_crtc_pll()
790 val = I915_READ(WRPLL_CTL2); in intel_ddi_put_crtc_pll()
885 WARN(I915_READ(reg) & WRPLL_PLL_ENABLE, in intel_ddi_pll_mode_set()
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Dintel_crt.c74 tmp = I915_READ(crt->adpa_reg); in intel_crt_get_hw_state()
96 temp = I915_READ(crt->adpa_reg); in intel_crt_set_dpms()
267 save_adpa = adpa = I915_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
276 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, in intel_ironlake_crt_detect_hotplug()
287 adpa = I915_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
306 save_adpa = adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
313 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, in valleyview_crt_detect_hotplug()
320 adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
365 hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); in intel_crt_detect_hotplug()
372 if (wait_for((I915_READ(PORT_HOTPLUG_EN) & in intel_crt_detect_hotplug()
[all …]
Dintel_display.c104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; in intel_pch_rawclk()
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; in intel_fdi_link_freq()
437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { in intel_dpio_read()
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { in intel_dpio_read()
450 return I915_READ(DPIO_DATA); in intel_dpio_read()
458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { in intel_dpio_write()
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) in intel_dpio_write()
903 frame = I915_READ(frame_reg); in ironlake_wait_for_vblank()
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); in intel_wait_for_vblank()
944 if (wait_for(I915_READ(pipestat_reg) & in intel_wait_for_vblank()
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Dintel_sprite.c55 sprctl = I915_READ(SPCNTR(pipe, plane)); in vlv_update_plane()
149 I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) & in vlv_disable_plane()
174 sprctl = I915_READ(SPCNTR(pipe, plane)); in vlv_update_colorkey()
196 key->min_value = I915_READ(SPKEYMINVAL(pipe, plane)); in vlv_get_colorkey()
197 key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane)); in vlv_get_colorkey()
198 key->channel_mask = I915_READ(SPKEYMSK(pipe, plane)); in vlv_get_colorkey()
200 sprctl = I915_READ(SPCNTR(pipe, plane)); in vlv_get_colorkey()
223 sprctl = I915_READ(SPRCTL(pipe)); in ivb_update_plane()
327 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); in ivb_disable_plane()
358 sprctl = I915_READ(SPRCTL(intel_plane->pipe)); in ivb_update_colorkey()
[all …]
Dintel_panel.c125 return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE; in is_backlight_combination_mode()
128 return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE; in is_backlight_combination_mode()
141 val = I915_READ(BLC_PWM_PCH_CTL2); in i915_read_blc_pwm_ctl()
149 val = I915_READ(BLC_PWM_CTL); in i915_read_blc_pwm_ctl()
154 I915_READ(BLC_PWM_CTL2); in i915_read_blc_pwm_ctl()
232 val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in intel_panel_get_backlight()
234 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in intel_panel_get_backlight()
254 u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in intel_pch_panel_set_backlight()
278 tmp = I915_READ(BLC_PWM_CTL); in intel_panel_actually_set_backlight()
309 I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE); in intel_panel_disable_backlight()
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Dintel_ringbuffer.h21 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
24 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
27 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
30 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
33 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
36 #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
37 #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
38 #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
Dintel_dp.c229 clkcfg = I915_READ(CLKCFG); in intel_hrawclk()
259 return (I915_READ(pp_stat_reg) & PP_ON) != 0; in ironlake_edp_have_panel_power()
269 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0; in ironlake_edp_have_panel_vdd()
288 I915_READ(pp_stat_reg), in intel_dp_check_edp()
289 I915_READ(pp_ctrl_reg)); in intel_dp_check_edp()
380 I915_READ(ch_ctl)); in intel_dp_aux_ch()
450 unpack_aux(I915_READ(ch_data + i), in intel_dp_aux_ch()
783 dpa_ctl = I915_READ(DP_A); in ironlake_set_pll_edp()
832 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; in intel_dp_mode_set()
929 I915_READ(pp_stat_reg), in ironlake_wait_panel_status()
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Dintel_lvds.c78 tmp = I915_READ(lvds_encoder->reg); in intel_lvds_get_hw_state()
106 temp = I915_READ(lvds_encoder->reg); in intel_pre_pll_enable_lvds()
195 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds()
197 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); in intel_enable_lvds()
199 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) in intel_enable_lvds()
222 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); in intel_disable_lvds()
223 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) in intel_disable_lvds()
226 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); in intel_disable_lvds()
325 if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) == in intel_lvds_compute_config()
1030 val = I915_READ(lvds_encoder->reg); in compute_is_dual_link_lvds()
[all …]
Dintel_dvo.c122 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_hw_state()
137 u32 temp = I915_READ(dvo_reg); in intel_disable_dvo()
141 I915_READ(dvo_reg); in intel_disable_dvo()
149 u32 temp = I915_READ(dvo_reg); in intel_enable_dvo()
152 I915_READ(dvo_reg); in intel_enable_dvo()
274 dvo_val = I915_READ(dvo_reg) & in intel_dvo_mode_set()
287 I915_WRITE(dpll_reg, I915_READ(dpll_reg) | DPLL_DVO_HIGH_SPEED); in intel_dvo_mode_set()
391 uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_current_mode()
Dintel_hdmi.c53 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
143 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_write_infoframe()
182 u32 val = I915_READ(reg); in ibx_write_infoframe()
220 u32 val = I915_READ(reg); in cpt_write_infoframe()
261 u32 val = I915_READ(reg); in vlv_write_infoframe()
300 u32 val = I915_READ(ctl_reg); in hsw_write_infoframe()
380 u32 val = I915_READ(reg); in g4x_set_infoframes()
445 u32 val = I915_READ(reg); in ibx_set_infoframes()
505 u32 val = I915_READ(reg); in cpt_set_infoframes()
540 u32 val = I915_READ(reg); in vlv_set_infoframes()
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Dintel_overlay.c277 tmp = I915_READ(DOVSTA); in intel_overlay_continue()
401 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) { in intel_overlay_release_old_vid()
831 … (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE) in check_overlay_possible_on_crtc()
841 u32 pfit_control = I915_READ(PFIT_CONTROL); in update_pfit_vscale_ratio()
849 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; in update_pfit_vscale_ratio()
852 ratio = I915_READ(PFIT_AUTO_RATIOS); in update_pfit_vscale_ratio()
854 ratio = I915_READ(PFIT_PGM_RATIOS); in update_pfit_vscale_ratio()
1014 pfit_control = I915_READ(PFIT_CONTROL); in intel_panel_fitter_pipe()
1255 attrs->gamma0 = I915_READ(OGAMC0); in intel_overlay_attrs()
1256 attrs->gamma1 = I915_READ(OGAMC1); in intel_overlay_attrs()
[all …]
Dintel_tv.c843 u32 tmp = I915_READ(TV_CTL); in intel_tv_get_hw_state()
859 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE); in intel_enable_tv()
868 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); in intel_disable_tv()
950 tv_ctl = I915_READ(TV_CTL); in intel_tv_mode_set()
1091 int pipeconf = I915_READ(pipeconf_reg); in intel_tv_mode_set()
1092 int dspcntr = I915_READ(dspcntr_reg); in intel_tv_mode_set()
1138 I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE); in intel_tv_mode_set()
1190 save_tv_dac = tv_dac = I915_READ(TV_DAC); in intel_tv_detect_type()
1191 save_tv_ctl = tv_ctl = I915_READ(TV_CTL); in intel_tv_detect_type()
1228 tv_dac = I915_READ(TV_DAC); in intel_tv_detect_type()
[all …]
Di915_sysfs.c44 raw_time = I915_READ(reg) * 128ULL; in calc_residency()
132 misccpctl = I915_READ(GEN7_MISCCPCTL); in i915_l3_read()
136 *((uint32_t *)(&buf[i])) = I915_READ(GEN7_L3LOG_BASE + i); in i915_l3_read()
253 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); in gt_max_freq_mhz_store()
309 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); in gt_min_freq_mhz_store()
351 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); in gt_rp_mhz_show()
Ddvo_ns2501.c101 ns->dvoc = I915_READ(DVO_C); in enable_dvo()
102 ns->pll_a = I915_READ(_DPLL_A); in enable_dvo()
103 ns->srcdim = I915_READ(DVOC_SRCDIM); in enable_dvo()
104 ns->fw_blc = I915_READ(FW_BLC); in enable_dvo()
Di915_gem_tiling.c99 dimm_c0 = I915_READ(MAD_DIMM_C0); in i915_gem_detect_bit_6_swizzle()
100 dimm_c1 = I915_READ(MAD_DIMM_C1); in i915_gem_detect_bit_6_swizzle()
138 dcc = I915_READ(DCC); in i915_gem_detect_bit_6_swizzle()
Di915_drv.c742 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); in i8xx_do_reset()
759 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); in i8xx_do_reset()
805 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); in ironlake_do_reset()
809 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); in ironlake_do_reset()
814 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); in ironlake_do_reset()
818 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); in ironlake_do_reset()
1327 reg->val = I915_READ(reg->offset); in i915_reg_read_ioctl()
Di915_gem_gtt.c108 ecobits = I915_READ(GAC_ECO_BITS); in gen6_ppgtt_enable()
112 gab_ctl = I915_READ(GAB_CTL); in gen6_ppgtt_enable()
115 ecochk = I915_READ(GAM_ECOCHK); in gen6_ppgtt_enable()
122 ecobits = I915_READ(GAC_ECO_BITS); in gen6_ppgtt_enable()
125 ecochk = I915_READ(GAM_ECOCHK); in gen6_ppgtt_enable()
Di915_gem_context.c110 reg = I915_READ(CXT_SIZE); in get_context_size()
114 reg = I915_READ(GEN7_CXT_SIZE); in get_context_size()
Dintel_sdvo.c245 I915_READ(intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
250 cval = I915_READ(GEN3_SDVOC); in intel_sdvo_write_sdvox()
252 bval = I915_READ(GEN3_SDVOB); in intel_sdvo_write_sdvox()
262 I915_READ(GEN3_SDVOB); in intel_sdvo_write_sdvox()
264 I915_READ(GEN3_SDVOC); in intel_sdvo_write_sdvox()
1194 sdvox = I915_READ(intel_sdvo->sdvo_reg); in intel_sdvo_mode_set()
1253 tmp = I915_READ(intel_sdvo->sdvo_reg); in intel_sdvo_get_hw_state()
1278 temp = I915_READ(intel_sdvo->sdvo_reg); in intel_disable_sdvo()
1319 temp = I915_READ(intel_sdvo->sdvo_reg); in intel_enable_sdvo()
Dintel_i2c.c77 val = I915_READ(DSPCLK_GATE_D); in intel_i2c_quirk_set()
301 val = I915_READ(GMBUS3 + reg_offset); in gmbus_xfer_read()

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