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Searched refs:ISR (Results 1 – 25 of 46) sorted by relevance

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/drivers/net/wireless/ath/wil6210/
DKconfig17 bool "Use Clear-On-Read mode for ISR registers for wil6210"
21 ISR registers on wil6210 chip may operate in either
25 For ISR debug, use W1C (say n); is allows to monitor ISR
26 registers with debugfs. If COR were used, ISR would
/drivers/staging/bcm/
DDebug.h87 #define ISR OTHERS macro
88 #define MP_DPC (ISR << 0)
/drivers/net/ethernet/realtek/
Datp.c616 int status = read_nibble(ioaddr, ISR); in atp_interrupt()
621 write_reg(ioaddr, ISR, ISR_RxOK); /* Clear the Rx interrupt. */ in atp_interrupt()
634 write_reg_high(ioaddr, ISR, ISRh_RxErr); in atp_interrupt()
647 write_reg(ioaddr, ISR, ISR_TxErr + ISR_TxOK); in atp_interrupt()
Datp.h38 ISR = 10, IMR = 11, /* Interrupt status and mask. */ enumerator
/drivers/rtc/
Drtc-at32ap700x.c101 alrm->pending = rtc_readl(rtc, ISR) & RTC_BIT(ISR_TOPI) ? 1 : 0; in at32_rtc_readalarm()
168 unsigned long isr = rtc_readl(rtc, ISR); in at32_rtc_interrupt()
/drivers/usb/serial/
Dio_16654.h37 #define ISR 2 // Interrupt Status Register (Read) macro
/drivers/net/ethernet/
Dfealnx.c174 ISR = 0x34, /* interrupt status */ enumerator
907 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR); in netdev_open()
1098 "config %8.8x.\n", dev->name, ioread32(ioaddr + ISR), in netdev_timer()
1169 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR); in enable_rxtx()
1209 dev->name, ioread32(ioaddr + ISR)); in fealnx_tx_timeout()
1448 u32 intr_status = ioread32(ioaddr + ISR); in intr_handler()
1451 iowrite32(intr_status, ioaddr + ISR); in intr_handler()
1601 dev->name, ioread32(ioaddr + ISR)); in intr_handler()
/drivers/net/irda/
Dw83977af_ir.h59 #define ISR 0x02 /* Interrupt status register */ macro
/drivers/net/ethernet/via/
Dvia-velocity.h995 volatile __le32 ISR; /* 0x24 */ member
1157 #define mac_read_isr(regs) readl(&((regs)->ISR))
1158 #define mac_write_isr(regs, x) writel((x),&((regs)->ISR))
1159 #define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR))
/drivers/video/i810/
Di810_regs.h47 #define ISR 0x020AC macro
/drivers/video/
Di740_reg.h232 #define ISR 0x3036 macro
/drivers/media/common/saa7146/
Dsaa7146_core.c300 ack_isr = isr = saa7146_read(dev, ISR); in interrupt_hw()
346 saa7146_write(dev, ISR, ack_isr); in interrupt_hw()
/drivers/net/ethernet/cadence/
Dmacb.c489 macb_writel(bp, ISR, MACB_BIT(TCOMP)); in macb_tx_interrupt()
717 status = macb_readl(bp, ISR); in macb_interrupt()
743 macb_writel(bp, ISR, MACB_BIT(RCOMP)); in macb_interrupt()
782 status = macb_readl(bp, ISR); in macb_interrupt()
979 macb_readl(bp, ISR); in macb_reset_hw()
Dat91_ether.c235 intstatus = macb_readl(lp, ISR); in at91ether_interrupt()
/drivers/block/rsxx/
Dcore.c137 isr = ioread32(card->regmap + ISR); in rsxx_isr()
459 st = ioread32(card->regmap + ISR); in rsxx_slot_reset()
Drsxx_priv.h190 ISR = 0x10, /* Interrupt Status Register */ enumerator
/drivers/atm/
Dfirestream.h295 #define ISR 0x64 macro
/drivers/staging/rtl8187se/
Dr8180_hw.h187 #define ISR 0x003C macro
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h243 ISR = 0x0f8, enumerator
Dr8192E_dev.c2239 tmp = read_nic_dword(dev, ISR); in rtl8192_ClearInterrupt()
2240 write_nic_dword(dev, ISR, tmp); in rtl8192_ClearInterrupt()
2267 *p_inta = read_nic_dword(dev, ISR); in rtl8192_interrupt_recognized()
2268 write_nic_dword(dev, ISR, *p_inta); in rtl8192_interrupt_recognized()
/drivers/staging/tidspbridge/Documentation/
Derror-codes39 - Unable to plug channel ISR for configured IRQ.
/drivers/net/wireless/rtlwifi/rtl8192se/
Dhw.c1560 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; in rtl92se_interrupt_recognized()
1561 rtl_write_dword(rtlpriv, ISR, *p_inta); in rtl92se_interrupt_recognized()
1563 *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1]; in rtl92se_interrupt_recognized()
1564 rtl_write_dword(rtlpriv, ISR + 4, *p_intb); in rtl92se_interrupt_recognized()
/drivers/net/wireless/ipw2x00/
DKconfig149 debug option enables debug on hot paths (e.g Tx, Rx, ISR) and
/drivers/char/pcmcia/
Dsynclink_cs.c280 #define ISR 0x3a macro
1186 isr = read_reg16(info, CHB + ISR); in mgslpc_isr()
1194 isr = read_reg16(info, CHA + ISR); in mgslpc_isr()
3271 read_reg16(info, CHA + ISR); /* clear pending IRQs */ in hdlc_mode()
3589 read_reg16(info, CHA + ISR); /* clear pending IRQs */ in async_mode()
/drivers/net/ethernet/natsemi/
Dns83820.c327 #define ISR 0x10 macro
1411 isr = readl(dev->base + ISR);
1582 isr = readl(dev->base + ISR);

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