| /drivers/gpu/drm/nouveau/core/engine/disp/ |
| D | dport.c | 53 u32 link_bw; member
74 DBG("%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw); in dp_set_link_config()
77 sink[0] = dp->link_bw / 27000; in dp_set_link_config()
87 while ((dp->link_bw / 10) < nv_ro16(bios, lnkcmp)) in dp_set_link_config()
91 while ((dp->link_bw / 27000) < nv_ro08(bios, lnkcmp)) in dp_set_link_config()
100 dp->link_nr, dp->link_bw / 27000, in dp_set_link_config()
272 const u32 *link_bw = bw_list; in nouveau_dp_train() local
308 while (*link_bw > (dp->dpcd[1] * 27000)) in nouveau_dp_train()
309 link_bw++; in nouveau_dp_train()
311 while (link_bw[0]) { in nouveau_dp_train()
[all …]
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| D | piornv50.c | 65 int head, int lane_nr, int link_bw, bool enh) in nv50_pior_dp_lnk_ctl() argument
72 ret = port->func->lnk_ctl(port, lane_nr, link_bw, enh); in nv50_pior_dp_lnk_ctl()
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| D | sornv94.c | 69 int head, int link_nr, int link_bw, bool enh_frame) in nv94_sor_dp_lnk_ctl() argument
82 if (link_bw > 0x06) in nv94_sor_dp_lnk_ctl()
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| D | sornvd0.c | 66 int head, int link_nr, int link_bw, bool enh_frame) in nvd0_sor_dp_lnk_ctl() argument
76 clksor |= link_bw << 18; in nvd0_sor_dp_lnk_ctl()
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| D | dport.h | 66 int link_nr, int link_bw, bool enh_frame);
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| D | nvd0.c | 764 u32 datarate, link_nr, link_bw, bits; in nvd0_disp_intr_unk2_2_tu() local
776 link_bw = (clksor & 0x007c0000) >> 18; in nvd0_disp_intr_unk2_2_tu()
777 link_bw *= 27000; in nvd0_disp_intr_unk2_2_tu()
781 do_div(ratio, link_nr * link_bw); in nvd0_disp_intr_unk2_2_tu()
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| D | nv50.c | 1012 u32 link_nr, link_bw, bits, r; in nv50_disp_intr_unk20_2_dp() local
1020 link_bw = 270000; in nv50_disp_intr_unk20_2_dp()
1022 link_bw = 162000; in nv50_disp_intr_unk20_2_dp()
1032 r = do_div(link_ratio, link_bw); in nv50_disp_intr_unk20_2_dp()
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| /drivers/gpu/drm/nouveau/ |
| D | nouveau_dp.c | 76 nv_encoder->dp.link_bw = 27000 * dpcd[1]; in nouveau_dp_detect()
80 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]); in nouveau_dp_detect()
83 nv_encoder->dcb->dpconf.link_bw); in nouveau_dp_detect()
87 if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw) in nouveau_dp_detect()
88 nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw; in nouveau_dp_detect()
91 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw); in nouveau_dp_detect()
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| D | nouveau_encoder.h | 59 int link_bw; member
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| D | nouveau_bios.c | 1475 entry->dpconf.link_bw = 162000; in parse_dcb20_entry()
1478 entry->dpconf.link_bw = 270000; in parse_dcb20_entry()
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| D | nouveau_connector.c | 836 max_clock *= nv_encoder->dp.link_bw; in nouveau_connector_mode_valid()
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| /drivers/gpu/drm/gma500/ |
| D | cdv_intel_dp.c | 68 uint8_t link_bw; member
163 cdv_intel_dp_link_clock(uint8_t link_bw) in cdv_intel_dp_link_clock() argument
165 if (link_bw == DP_LINK_BW_2_7) in cdv_intel_dp_link_clock()
721 intel_dp->link_bw = bws[clock]; in cdv_intel_dp_mode_fixup()
723 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); in cdv_intel_dp_mode_fixup()
726 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
735 intel_dp->link_bw = bws[max_clock]; in cdv_intel_dp_mode_fixup()
736 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); in cdv_intel_dp_mode_fixup()
739 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
875 intel_dp->link_configuration[0] = intel_dp->link_bw; in cdv_intel_dp_mode_set()
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| /drivers/gpu/drm/ |
| D | drm_dp_helper.c | 336 int drm_dp_bw_code_to_link_rate(u8 link_bw) in drm_dp_bw_code_to_link_rate() argument
338 switch (link_bw) { in drm_dp_bw_code_to_link_rate()
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| /drivers/gpu/drm/nouveau/core/subdev/i2c/ |
| D | anx9805.c | 34 anx9805_train(struct nouveau_i2c_port *port, int link_nr, int link_bw, bool enh) in anx9805_train() argument
40 nv_wri2cr(mast, chan->addr, 0xa0, link_bw); in anx9805_train()
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| /drivers/gpu/drm/nouveau/core/include/subdev/bios/ |
| D | dcb.h | 50 int link_bw; member
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| /drivers/gpu/drm/i915/ |
| D | intel_drv.h | 408 uint8_t link_bw; member
609 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
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| D | intel_ddi.c | 846 switch (intel_dp->link_bw) { in intel_ddi_pll_mode_set()
858 intel_dp->link_bw); in intel_ddi_pll_mode_set()
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| D | intel_dp.c | 742 intel_dp->link_bw = bws[clock]; in intel_dp_compute_config()
744 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); in intel_dp_compute_config()
749 intel_dp->link_bw, intel_dp->lane_count, in intel_dp_compute_config()
764 intel_dp->link_configuration[0] = intel_dp->link_bw; in intel_dp_init_link_config()
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| D | intel_display.c | 5413 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) in ironlake_get_lanes_required() argument
5421 return bps / (link_bw * 8) + 1; in ironlake_get_lanes_required()
5465 int target_clock, lane, link_bw; in ironlake_fdi_set_m_n() local
5474 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; in ironlake_fdi_set_m_n()
5481 lane = ironlake_get_lanes_required(target_clock, link_bw, in ironlake_fdi_set_m_n()
5487 link_bw *= intel_crtc->config.pixel_multiplier; in ironlake_fdi_set_m_n()
5489 link_bw, &m_n); in ironlake_fdi_set_m_n()
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