| /drivers/video/riva/ |
| D | nvreg.h | 31 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask) argument
34 #define SetBF(mask,value) ((value) << (0?mask)) argument
35 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) ) argument
37 #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ argument
38 | SetBF(mask,value)))
51 #define DEVICE_DEF(device,mask,value) \ argument
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
53 #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) argument
54 #define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask) argument
59 #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) argument
[all …]
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| /drivers/mfd/ |
| D | sec-irq.c | 28 .mask = S2MPS11_IRQ_PWRONF_MASK,
32 .mask = S2MPS11_IRQ_PWRONR_MASK,
36 .mask = S2MPS11_IRQ_JIGONBF_MASK,
40 .mask = S2MPS11_IRQ_JIGONBR_MASK,
44 .mask = S2MPS11_IRQ_ACOKBF_MASK,
48 .mask = S2MPS11_IRQ_ACOKBR_MASK,
52 .mask = S2MPS11_IRQ_PWRON1S_MASK,
56 .mask = S2MPS11_IRQ_MRB_MASK,
60 .mask = S2MPS11_IRQ_RTC60S_MASK,
64 .mask = S2MPS11_IRQ_RTCA1_MASK,
[all …]
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| D | wm8350-irq.c | 43 int mask; member
51 .mask = WM8350_OC_LS_EINT,
57 .mask = WM8350_UV_DC1_EINT,
62 .mask = WM8350_UV_DC2_EINT,
67 .mask = WM8350_UV_DC3_EINT,
72 .mask = WM8350_UV_DC4_EINT,
77 .mask = WM8350_UV_DC5_EINT,
82 .mask = WM8350_UV_DC6_EINT,
87 .mask = WM8350_UV_LDO1_EINT,
92 .mask = WM8350_UV_LDO2_EINT,
[all …]
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| D | wm8994-irq.c | 32 .mask = WM8994_TEMP_SHUT_EINT,
36 .mask = WM8994_MIC1_DET_EINT,
40 .mask = WM8994_MIC1_SHRT_EINT,
44 .mask = WM8994_MIC2_DET_EINT,
48 .mask = WM8994_MIC2_SHRT_EINT,
52 .mask = WM8994_FLL1_LOCK_EINT,
56 .mask = WM8994_FLL2_LOCK_EINT,
60 .mask = WM8994_SRC1_LOCK_EINT,
64 .mask = WM8994_SRC2_LOCK_EINT,
68 .mask = WM8994_AIF1DRC1_SIG_DET,
[all …]
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| D | wm831x-irq.c | 33 int mask; member
40 .mask = WM831X_TEMP_THW_EINT,
45 .mask = WM831X_GP1_EINT,
50 .mask = WM831X_GP2_EINT,
55 .mask = WM831X_GP3_EINT,
60 .mask = WM831X_GP4_EINT,
65 .mask = WM831X_GP5_EINT,
70 .mask = WM831X_GP6_EINT,
75 .mask = WM831X_GP7_EINT,
80 .mask = WM831X_GP8_EINT,
[all …]
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| D | da9052-irq.c | 41 .mask = DA9052_IRQ_MASK_POS_1,
45 .mask = DA9052_IRQ_MASK_POS_2,
49 .mask = DA9052_IRQ_MASK_POS_3,
53 .mask = DA9052_IRQ_MASK_POS_4,
57 .mask = DA9052_IRQ_MASK_POS_5,
61 .mask = DA9052_IRQ_MASK_POS_6,
65 .mask = DA9052_IRQ_MASK_POS_7,
69 .mask = DA9052_IRQ_MASK_POS_8,
73 .mask = DA9052_IRQ_MASK_POS_1,
77 .mask = DA9052_IRQ_MASK_POS_2,
[all …]
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| D | tps65910.c | 59 .mask = INT_MSK_PWRHOLD_F_IT_MSK_MASK,
63 .mask = INT_MSK_VMBHI_IT_MSK_MASK,
67 .mask = INT_MSK_PWRON_IT_MSK_MASK,
71 .mask = INT_MSK_PWRON_LP_IT_MSK_MASK,
75 .mask = INT_MSK_PWRHOLD_R_IT_MSK_MASK,
79 .mask = INT_MSK_HOTDIE_IT_MSK_MASK,
83 .mask = INT_MSK_RTC_ALARM_IT_MSK_MASK,
87 .mask = INT_MSK_RTC_PERIOD_IT_MSK_MASK,
93 .mask = INT_MSK2_GPIO0_R_IT_MSK_MASK,
97 .mask = INT_MSK2_GPIO0_F_IT_MSK_MASK,
[all …]
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| D | max8998-irq.c | 21 int mask; member
27 .mask = MAX8998_IRQ_DCINF_MASK,
31 .mask = MAX8998_IRQ_DCINR_MASK,
35 .mask = MAX8998_IRQ_JIGF_MASK,
39 .mask = MAX8998_IRQ_JIGR_MASK,
43 .mask = MAX8998_IRQ_PWRONF_MASK,
47 .mask = MAX8998_IRQ_PWRONR_MASK,
51 .mask = MAX8998_IRQ_WTSREVNT_MASK,
55 .mask = MAX8998_IRQ_SMPLEVNT_MASK,
59 .mask = MAX8998_IRQ_ALARM1_MASK,
[all …]
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| D | palmas.c | 123 .mask = PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV,
126 .mask = PALMAS_INT1_STATUS_PWRON,
129 .mask = PALMAS_INT1_STATUS_LONG_PRESS_KEY,
132 .mask = PALMAS_INT1_STATUS_RPWRON,
135 .mask = PALMAS_INT1_STATUS_PWRDOWN,
138 .mask = PALMAS_INT1_STATUS_HOTDIE,
141 .mask = PALMAS_INT1_STATUS_VSYS_MON,
144 .mask = PALMAS_INT1_STATUS_VBAT_MON,
148 .mask = PALMAS_INT2_STATUS_RTC_ALARM,
152 .mask = PALMAS_INT2_STATUS_RTC_TIMER,
[all …]
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| D | wm5110-tables.c | 246 [ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 },
247 [ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 },
248 [ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 },
249 [ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 },
266 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
267 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
268 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
269 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
272 .reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1
275 .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
[all …]
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| D | max8907.c | 118 { .reg_offset = 0, .mask = 1 << 0, },
119 { .reg_offset = 0, .mask = 1 << 1, },
120 { .reg_offset = 0, .mask = 1 << 2, },
121 { .reg_offset = 1, .mask = 1 << 0, },
122 { .reg_offset = 1, .mask = 1 << 1, },
123 { .reg_offset = 1, .mask = 1 << 2, },
124 { .reg_offset = 1, .mask = 1 << 3, },
125 { .reg_offset = 1, .mask = 1 << 4, },
126 { .reg_offset = 1, .mask = 1 << 5, },
127 { .reg_offset = 1, .mask = 1 << 6, },
[all …]
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| D | wm5102-tables.c | 113 .mask = ARIZONA_MICD_CLAMP_FALL_EINT1
116 .mask = ARIZONA_MICD_CLAMP_RISE_EINT1
118 [ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 },
119 [ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 },
120 [ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 },
121 [ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 },
137 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
138 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
139 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
140 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
[all …]
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| /drivers/gpio/ |
| D | gpio-vr41xx.c | 215 u16 mask; in vr41xx_set_irq_trigger() local
218 mask = 1 << pin; in vr41xx_set_irq_trigger()
220 giu_set(GIUINTTYPL, mask); in vr41xx_set_irq_trigger()
222 giu_set(GIUINTHTSELL, mask); in vr41xx_set_irq_trigger()
224 giu_clear(GIUINTHTSELL, mask); in vr41xx_set_irq_trigger()
228 giu_set(GIUFEDGEINHL, mask); in vr41xx_set_irq_trigger()
229 giu_clear(GIUREDGEINHL, mask); in vr41xx_set_irq_trigger()
232 giu_clear(GIUFEDGEINHL, mask); in vr41xx_set_irq_trigger()
233 giu_set(GIUREDGEINHL, mask); in vr41xx_set_irq_trigger()
236 giu_set(GIUFEDGEINHL, mask); in vr41xx_set_irq_trigger()
[all …]
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| /drivers/video/ |
| D | c2p_core.h | 21 unsigned int shift, u32 mask) in _transp() argument
23 u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; in _transp()
62 u32 mask = get_mask(n); in transp8() local
67 _transp(d, 0, 1, n, mask); in transp8()
69 _transp(d, 2, 3, n, mask); in transp8()
71 _transp(d, 4, 5, n, mask); in transp8()
73 _transp(d, 6, 7, n, mask); in transp8()
78 _transp(d, 0, 2, n, mask); in transp8()
79 _transp(d, 1, 3, n, mask); in transp8()
81 _transp(d, 4, 6, n, mask); in transp8()
[all …]
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| D | fb_draw.h | 14 comp(unsigned long a, unsigned long b, unsigned long mask) in comp() argument
16 return ((a ^ b) & mask) ^ b; in comp()
103 u32 mask; in fb_shifted_pixels_mask_u32() local
106 mask = FB_SHIFT_HIGH(p, ~(u32)0, index); in fb_shifted_pixels_mask_u32()
108 mask = 0xff << FB_LEFT_POS(p, 8); in fb_shifted_pixels_mask_u32()
109 mask = FB_SHIFT_LOW(p, mask, index & (bswapmask)) & mask; in fb_shifted_pixels_mask_u32()
110 mask = FB_SHIFT_HIGH(p, mask, index & ~(bswapmask)); in fb_shifted_pixels_mask_u32()
115 mask |= FB_SHIFT_HIGH(p, ~(u32)0, in fb_shifted_pixels_mask_u32()
118 return mask; in fb_shifted_pixels_mask_u32()
125 unsigned long mask; in fb_shifted_pixels_mask_long() local
[all …]
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| D | atafb_iplan2p8.c | 114 u32 pval[4], v, v1, mask; in atafb_iplan2p8_copyarea() local
120 mask = 0xff00ff00; in atafb_iplan2p8_copyarea()
135 pval[0] = (*src32++ << 8) & mask; in atafb_iplan2p8_copyarea()
136 pval[1] = (*src32++ << 8) & mask; in atafb_iplan2p8_copyarea()
137 pval[2] = (*src32++ << 8) & mask; in atafb_iplan2p8_copyarea()
138 pval[3] = (*src32++ << 8) & mask; in atafb_iplan2p8_copyarea()
140 pval[0] = dst32[0] & mask; in atafb_iplan2p8_copyarea()
141 pval[1] = dst32[1] & mask; in atafb_iplan2p8_copyarea()
142 pval[2] = dst32[2] & mask; in atafb_iplan2p8_copyarea()
143 pval[3] = dst32[3] & mask; in atafb_iplan2p8_copyarea()
[all …]
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| /drivers/media/pci/ivtv/ |
| D | ivtv-gpio.c | 161 u16 mask, data; in subdev_s_clock_freq() local
163 mask = itv->card->gpio_audio_freq.mask; in subdev_s_clock_freq()
176 if (mask) in subdev_s_clock_freq()
177 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); in subdev_s_clock_freq()
184 u16 mask; in subdev_g_tuner() local
186 mask = itv->card->gpio_audio_detect.mask; in subdev_g_tuner()
187 if (mask == 0 || (read_reg(IVTV_REG_GPIO_IN) & mask)) in subdev_g_tuner()
198 u16 mask, data; in subdev_s_tuner() local
200 mask = itv->card->gpio_audio_mode.mask; in subdev_s_tuner()
217 if (mask) in subdev_s_tuner()
[all …]
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| /drivers/input/joystick/ |
| D | analog.c | 110 int mask; member
119 unsigned char mask; member
183 if (analog->mask & ANALOG_HAT_FCS) in analog_decode()
191 if (analog->mask & (0x10 << i)) in analog_decode()
194 if (analog->mask & ANALOG_HBTN_CHF) in analog_decode()
198 if (analog->mask & ANALOG_BTN_TL) in analog_decode()
200 if (analog->mask & ANALOG_BTN_TR) in analog_decode()
202 if (analog->mask & ANALOG_BTN_TL2) in analog_decode()
204 if (analog->mask & ANALOG_BTN_TR2) in analog_decode()
208 if (analog->mask & (1 << i)) in analog_decode()
[all …]
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| /drivers/pinctrl/spear/ |
| D | pinctrl-spear320.c | 37 .mask = 0x00000007,
45 .mask = 0x00000007,
53 .mask = 0x00000007,
61 .mask = 0x00000007,
69 .mask = 0x00000001,
466 .mask = PMX_PL_69_MASK,
470 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
478 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
484 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
523 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
[all …]
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| D | pinctrl-spear1340.c | 220 .mask = PADS_AS_GPIO_REG0_MASK,
224 .mask = PADS_AS_GPIO_REGS_MASK,
228 .mask = PADS_AS_GPIO_REGS_MASK,
232 .mask = PADS_AS_GPIO_REGS_MASK,
236 .mask = PADS_AS_GPIO_REGS_MASK,
240 .mask = PADS_AS_GPIO_REGS_MASK,
244 .mask = PADS_AS_GPIO_REGS_MASK,
248 .mask = PADS_AS_GPIO_REG7_MASK,
281 .mask = FSMC_8BIT_REG7_MASK,
306 .mask = KBD_ROW_COL_MASK,
[all …]
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| D | pinctrl-spear1310.c | 242 .mask = PMX_I2C0_MASK,
246 .mask = PMX_I2C0_MASK,
278 .mask = PMX_SSP0_MASK,
282 .mask = PMX_SSP0_MASK,
307 .mask = PMX_SSP0_CS0_MASK,
311 .mask = PMX_SSP0_CS0_MASK,
336 .mask = PMX_SSP0_CS1_2_MASK,
340 .mask = PMX_SSP0_CS1_2_MASK,
373 .mask = PMX_I2S0_MASK,
377 .mask = PMX_I2S0_MASK,
[all …]
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| /drivers/staging/zcache/ramster/ |
| D | masklog.h | 134 #define __mlog_test_u64(mask, bits) \ argument
135 ((u32)(mask & 0xffffffff) & bits.words[0] || \
136 ((u64)(mask) >> 32) & bits.words[1])
137 #define __mlog_set_u64(mask, bits) do { \ argument
138 bits.words[0] |= (u32)(mask & 0xffffffff); \
139 bits.words[1] |= (u64)(mask) >> 32; \
141 #define __mlog_clear_u64(mask, bits) do { \ argument
142 bits.words[0] &= ~((u32)(mask & 0xffffffff)); \
143 bits.words[1] &= ~((u64)(mask) >> 32); \
145 #define MLOG_BITS_RHS(mask) { \ argument
[all …]
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| /drivers/pinctrl/ |
| D | pinctrl-at91.c | 141 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
142 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
143 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
144 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
145 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
147 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool in_on);
149 void (*set_debounce)(void __iomem *pio, unsigned mask, bool in_on, u32 div);
151 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool in_on);
153 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
321 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) in at91_mux_disable_interrupt() argument
[all …]
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| /drivers/block/drbd/ |
| D | drbd_state.h | 37 ({ union drbd_state mask; mask.i = 0; mask.T = T##_MASK; mask; }), \
40 ({ union drbd_state mask; mask.i = 0; mask.T1 = T1##_MASK; \
41 mask.T2 = T2##_MASK; mask; }), \
45 ({ union drbd_state mask; mask.i = 0; mask.T1 = T1##_MASK; \
46 mask.T2 = T2##_MASK; mask.T3 = T3##_MASK; mask; }), \
112 union drbd_state mask,
127 _conn_request_state(struct drbd_tconn *tconn, union drbd_state mask, union drbd_state val,
131 conn_request_state(struct drbd_tconn *tconn, union drbd_state mask, union drbd_state val,
148 union drbd_state mask, in drbd_request_state() argument
151 return _drbd_request_state(mdev, mask, val, CS_VERBOSE + CS_ORDERED); in drbd_request_state()
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| /drivers/infiniband/hw/qib/ |
| D | qib_twsi.c | 91 u32 mask; in scl_out() local
95 mask = 1UL << dd->gpio_scl_num; in scl_out()
98 dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask); in scl_out()
109 if (mask & dd->f_gpio_mod(dd, 0, 0, 0)) in scl_out()
122 u32 mask; in sda_out() local
124 mask = 1UL << dd->gpio_sda_num; in sda_out()
127 dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask); in sda_out()
136 u32 read_val, mask; in sda_in() local
139 mask = (1UL << bnum); in sda_in()
141 dd->f_gpio_mod(dd, 0, 0, mask); in sda_in()
[all …]
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