1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/fpu.h>
24 #include <asm/mipsregs.h>
25 #include <asm/msa.h>
26 #include <asm/watch.h>
27 #include <asm/elf.h>
28 #include <asm/spram.h>
29 #include <asm/uaccess.h>
30
31 /* Hardware capabilities */
32 #ifdef CONFIG_CPU_MIPSR6
33 unsigned int elf_hwcap __read_mostly = HWCAP_MIPS_R6;
34 #else
35 unsigned int elf_hwcap __read_mostly;
36 #endif
37
38 static int __cpuinitdata mips_fpu_disabled;
39
fpu_disable(char * s)40 static int __init fpu_disable(char *s)
41 {
42 cpu_data[0].options &= ~MIPS_CPU_FPU;
43 mips_fpu_disabled = 1;
44
45 return 1;
46 }
47
48 __setup("nofpu", fpu_disable);
49
50 int __cpuinitdata mips_dsp_disabled;
51
dsp_disable(char * s)52 static int __init dsp_disable(char *s)
53 {
54 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
55 mips_dsp_disabled = 1;
56
57 return 1;
58 }
59
60 __setup("nodsp", dsp_disable);
61
62 static int mips_htw_disabled;
63
htw_disable(char * s)64 static int __init htw_disable(char *s)
65 {
66 mips_htw_disabled = 1;
67 if (cpu_has_htw) {
68 write_c0_pwctl(HTW_PWCTL_BASE);
69 cpu_data[0].options2 &= ~MIPS_CPU_HTW;
70 }
71 return 1;
72 }
73
74 __setup("nohtw", htw_disable);
75
check_errata(void)76 static inline void check_errata(void)
77 {
78 struct cpuinfo_mips *c = ¤t_cpu_data;
79
80 switch (c->cputype) {
81 case CPU_34K:
82 /*
83 * Erratum "RPS May Cause Incorrect Instruction Execution"
84 * This code only handles VPE0, any SMP/SMTC/RTOS code
85 * making use of VPE1 will be responsable for that VPE.
86 */
87 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
88 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
89 break;
90 default:
91 break;
92 }
93 }
94
check_bugs32(void)95 void __init check_bugs32(void)
96 {
97 check_errata();
98 }
99
100 #include <asm/pgtable.h>
101 #include <asm/bootinfo.h>
102 /*
103 * Probe whether cpu has config register by trying to play with
104 * alternate cache bit and see whether it matters.
105 * It's used by cpu_probe to distinguish between R3000A and R3081.
106 */
cpu_has_confreg(void)107 static inline int cpu_has_confreg(void)
108 {
109 #ifdef CONFIG_CPU_R3000
110 extern unsigned long r3k_cache_size(unsigned long);
111 unsigned long size1, size2;
112 unsigned long cfg = read_c0_conf();
113
114 size1 = r3k_cache_size(ST0_ISC);
115 write_c0_conf(cfg ^ R30XX_CONF_AC);
116 size2 = r3k_cache_size(ST0_ISC);
117 write_c0_conf(cfg);
118 return size1 != size2;
119 #else
120 return 0;
121 #endif
122 }
123
set_elf_platform(int cpu,const char * plat)124 static inline void set_elf_platform(int cpu, const char *plat)
125 {
126 if (cpu == 0)
127 __elf_platform = plat;
128 }
129
130 /*
131 * Get the FPU Implementation/Revision.
132 */
cpu_get_fpu_id(void)133 static inline unsigned long cpu_get_fpu_id(void)
134 {
135 unsigned long tmp, fpu_id;
136
137 tmp = read_c0_status();
138 __enable_fpu();
139 fpu_id = read_32bit_cp1_register(CP1_REVISION);
140 write_c0_status(tmp);
141 return fpu_id;
142 }
143
144 /*
145 * Set and Get the FPU CSR31.
146 */
cpu_test_fpu_csr31(unsigned long fcr31)147 static inline unsigned long cpu_test_fpu_csr31(unsigned long fcr31)
148 {
149 unsigned long tmp;
150
151 tmp = read_c0_status();
152 __enable_fpu();
153 write_32bit_cp1_register(CP1_STATUS,fcr31);
154 enable_fpu_hazard();
155 fcr31 = read_32bit_cp1_register(CP1_STATUS);
156 write_c0_status(tmp);
157 return fcr31;
158 }
159
160 /*
161 * Check the CPU has an FPU the official way.
162 */
__cpu_has_fpu(void)163 static inline int __cpu_has_fpu(void)
164 {
165 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
166 }
167
cpu_get_msa_id(void)168 static inline unsigned long cpu_get_msa_id(void)
169 {
170 unsigned long status, msa_id;
171
172 status = read_c0_status();
173 set_c0_status(ST0_CU1|ST0_FR);
174 enable_fpu_hazard();
175 clear_c0_config5(MIPS_CONF5_FRE);
176 enable_msa();
177 msa_id = read_msa_ir();
178 disable_msa();
179 write_c0_status(status);
180 return msa_id;
181 }
182
cpu_probe_vmbits(struct cpuinfo_mips * c)183 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
184 {
185 #ifdef __NEED_VMBITS_PROBE
186 write_c0_entryhi(0x3fffffffffffe000ULL);
187 back_to_back_c0_hazard();
188 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
189 #endif
190 }
191
cpu_probe_pabits(struct cpuinfo_mips * c)192 static inline void cpu_probe_pabits(struct cpuinfo_mips *c)
193 {
194 unsigned int enlow;
195
196 write_c0_entrylo0((-1UL)>>2); /* skip RIXI bits */
197 back_to_back_c0_hazard();
198 enlow = read_c0_entrylo0();
199 if ((_MIPS_SZLONG - fls(enlow)) < ilog2(_PAGE_GLOBAL))
200 c->options2 |= MIPS_CPU_HIMEM;
201 }
202
set_isa(struct cpuinfo_mips * c,unsigned int isa)203 static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa)
204 {
205 switch (isa) {
206 case MIPS_CPU_ISA_M64R2:
207 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
208 case MIPS_CPU_ISA_M64R1:
209 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
210 case MIPS_CPU_ISA_V:
211 c->isa_level |= MIPS_CPU_ISA_V;
212 case MIPS_CPU_ISA_IV:
213 c->isa_level |= MIPS_CPU_ISA_IV;
214 case MIPS_CPU_ISA_III:
215 c->isa_level |= MIPS_CPU_ISA_I | MIPS_CPU_ISA_II |
216 MIPS_CPU_ISA_III;
217 break;
218
219 case MIPS_CPU_ISA_M32R2:
220 c->isa_level |= MIPS_CPU_ISA_M32R2;
221 case MIPS_CPU_ISA_M32R1:
222 c->isa_level |= MIPS_CPU_ISA_M32R1;
223 case MIPS_CPU_ISA_II:
224 c->isa_level |= MIPS_CPU_ISA_II;
225 case MIPS_CPU_ISA_I:
226 c->isa_level |= MIPS_CPU_ISA_I;
227 break;
228 }
229 }
230
report_kernel(void)231 static void report_kernel(void)
232 {
233 printk("Kernel:");
234 #ifdef CONFIG_CPU_BIG_ENDIAN
235 printk(" EB");
236 #endif
237 #ifdef CONFIG_CPU_LITTLE_ENDIAN
238 printk(" EL");
239 #endif
240 #ifdef CONFIG_64BIT
241 printk(" 64bit, 64bit address");
242 #ifdef CONFIG_48VMBITS
243 printk(", 48 segbits");
244 #else
245 printk(", 40 segbits");
246 #endif
247 #elif defined(CONFIG_CPU_MIPS64)
248 printk(" 64bit, 32bit address");
249 #else
250 printk(" 32bit");
251 #endif
252 #ifdef CONFIG_CPU_MIPSR6
253 printk(", R6");
254 #endif
255 #ifdef CONFIG_CPU_HAS_MSA
256 printk(", MSA");
257 #endif
258 #ifdef CONFIG_MIPS_HARDWARE_TRACE
259 printk(", HW trace");
260 #endif
261 #ifdef CONFIG_NO_HZ_IDLE
262 printk(", dynamic ticks");
263 #else
264 printk(", periodic ticks");
265 #endif
266 printk(" %dHz",CONFIG_HZ);
267 #ifdef CONFIG_HIGH_RES_TIMERS
268 printk(", HiRes timers");
269 #endif
270 #ifdef CONFIG_DMA_COHERENT
271 printk(", coherent DMA");
272 #endif
273 #ifdef CONFIG_DMA_NONCOHERENT
274 printk(", non-coherent DMA");
275 #endif
276 printk(", pagesize=%dKiB\n",(1 << (PAGE_SHIFT - 10)));
277 }
278
279 static char unknown_isa[] __cpuinitdata = KERN_ERR \
280 "Unsupported ISA type, c0.config0: %d.";
281
decode_config0(struct cpuinfo_mips * c)282 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
283 {
284 unsigned int config0;
285 int isa;
286
287 config0 = read_c0_config();
288
289 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
290 c->options |= MIPS_CPU_TLB;
291 if (((config0 & MIPS_CONF_MT) >> 7) == 4)
292 c->options |= MIPS_CPU_TLB;
293 isa = (config0 & MIPS_CONF_AT) >> 13;
294 switch (isa) {
295 case 0:
296 switch ((config0 & MIPS_CONF_AR) >> 10) {
297 case 0:
298 set_isa(c, MIPS_CPU_ISA_M32R1);
299 break;
300 case 1:
301 set_isa(c, MIPS_CPU_ISA_M32R2);
302 break;
303 case 2:
304 c->isa_level = MIPS_CPU_ISA_M32R6;
305 break;
306 default:
307 goto unknown;
308 }
309 break;
310 case 2:
311 switch ((config0 & MIPS_CONF_AR) >> 10) {
312 case 0:
313 set_isa(c, MIPS_CPU_ISA_M64R1);
314 break;
315 case 1:
316 set_isa(c, MIPS_CPU_ISA_M64R2);
317 break;
318 case 2:
319 c->isa_level = MIPS_CPU_ISA_M64R6;
320 break;
321 }
322 break;
323 default:
324 goto unknown;
325 }
326
327 return config0 & MIPS_CONF_M;
328
329 unknown:
330 panic(unknown_isa, config0);
331 }
332
decode_config1(struct cpuinfo_mips * c)333 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
334 {
335 unsigned int config1;
336
337 config1 = read_c0_config1();
338
339 if (config1 & MIPS_CONF1_MD)
340 c->ases |= MIPS_ASE_MDMX;
341 if (config1 & MIPS_CONF1_WR)
342 c->options |= MIPS_CPU_WATCH;
343 if (config1 & MIPS_CONF1_CA)
344 c->ases |= MIPS_ASE_MIPS16;
345 if (config1 & MIPS_CONF1_EP)
346 c->options |= MIPS_CPU_EJTAG;
347 if (config1 & MIPS_CONF1_FP) {
348 c->options |= MIPS_CPU_FPU;
349 c->options |= MIPS_CPU_32FPR;
350 }
351 if (cpu_has_tlb) {
352 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
353 c->tlbsizevtlb = c->tlbsize;
354 c->tlbsizeftlbsets = 0;
355 }
356
357 return config1 & MIPS_CONF_M;
358 }
359
decode_config2(struct cpuinfo_mips * c)360 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
361 {
362 unsigned int config2;
363
364 config2 = read_c0_config2();
365
366 if (config2 & MIPS_CONF2_SL)
367 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
368
369 return config2 & MIPS_CONF_M;
370 }
371
decode_config3(struct cpuinfo_mips * c)372 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
373 {
374 unsigned int config3;
375
376 config3 = read_c0_config3();
377
378 if (config3 & MIPS_CONF3_SM) {
379 c->ases |= MIPS_ASE_SMARTMIPS;
380 #if defined(CONFIG_64BIT) || !defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
381 c->options |= MIPS_CPU_RIXI;
382 #endif
383 }
384 #if defined(CONFIG_64BIT) || !defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
385 if (config3 & MIPS_CONF3_RXI)
386 c->options |= MIPS_CPU_RIXI;
387 #endif
388 if (config3 & MIPS_CONF3_DSP)
389 c->ases |= MIPS_ASE_DSP;
390 if (config3 & MIPS_CONF3_DSP2P)
391 c->ases |= MIPS_ASE_DSP2P;
392 if (config3 & MIPS_CONF3_VINT)
393 c->options |= MIPS_CPU_VINT;
394 if (config3 & MIPS_CONF3_VEIC)
395 c->options |= MIPS_CPU_VEIC;
396 if (config3 & MIPS_CONF3_MT)
397 c->ases |= MIPS_ASE_MIPSMT;
398 if (config3 & MIPS_CONF3_ULRI)
399 c->options |= MIPS_CPU_ULRI;
400 if (config3 & MIPS_CONF3_ISA)
401 c->options |= MIPS_CPU_MICROMIPS;
402 #ifdef CONFIG_CPU_MICROMIPS
403 write_c0_config3(read_c0_config3() | MIPS_CONF3_ISA_OE);
404 #endif
405 if (config3 & MIPS_CONF3_VZ)
406 c->ases |= MIPS_ASE_VZ;
407 if (config3 & MIPS_CONF3_SC)
408 c->options |= MIPS_CPU_SEGMENTS;
409 /* Only tested on 32-bit cores */
410 if (config3 & MIPS_CONF3_PW && !config_enabled(CONFIG_MIPS_PGD_C0_CONTEXT))
411 c->options2 |= MIPS_CPU_HTW;
412 if (config3 & MIPS_CONF3_MSA)
413 c->ases |= MIPS_ASE_MSA;
414
415 return config3 & MIPS_CONF_M;
416 }
417
418 static unsigned int cpu_capability = 0;
419
decode_config4(struct cpuinfo_mips * c,int pass,int conf6available)420 static inline unsigned int decode_config4(struct cpuinfo_mips *c, int pass,
421 int conf6available)
422 {
423 unsigned int config4;
424 unsigned int newcf4;
425 unsigned int config6;
426
427 config4 = read_c0_config4();
428
429 if (pass && cpu_has_tlb) {
430 if (config4 & MIPS_CONF4_IE) {
431 if (config4 & MIPS_CONF4_TLBINV) {
432 c->options |= MIPS_CPU_TLBINV;
433 printk("TLBINV/F supported, config4=0x%0x\n",config4);
434 if (config4 & MIPS_CONF4_TLBINV_FULL)
435 c->options |= MIPS_CPU_TLBINV_FULL;
436 }
437 }
438 #ifdef CONFIG_CPU_MIPSR6
439 c->tlbsizevtlb = ((c->tlbsizevtlb - 1) |
440 (((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
441 MIPS_CONF4_VTLBSIZEEXT_SHIFT) <<
442 MIPS_CONF1_TLBS_SIZE)) + 1;
443 c->tlbsize = c->tlbsizevtlb;
444
445 newcf4 = (config4 & ~MIPS_CONF4_FTLBPAGESIZE) |
446 ((((fls(PAGE_SIZE >> BASIC_PAGE_SHIFT)-1)/2)+1) <<
447 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
448 write_c0_config4(newcf4);
449 back_to_back_c0_hazard();
450 config4 = read_c0_config4();
451 if (config4 != newcf4) {
452 printk(KERN_ERR "PAGE_SIZE 0x%0lx is not supported by FTLB (config4=0x%0x)\n",
453 PAGE_SIZE, config4);
454 if (conf6available && (cpu_capability & MIPS_FTLB_CAPABLE)) {
455 printk("Switching FTLB OFF\n");
456 config6 = read_c0_config6();
457 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
458 }
459 printk("Total TLB(VTLB) inuse: %d\n",c->tlbsizevtlb);
460 } else {
461 c->tlbsizeftlbsets = 1 <<
462 ((config4 & MIPS_CONF4_FTLBSETS) >>
463 MIPS_CONF4_FTLBSETS_SHIFT);
464 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
465 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
466 c->tlbsize += (c->tlbsizeftlbways *
467 c->tlbsizeftlbsets);
468 printk("V/FTLB found: VTLB=%d, FTLB sets=%d, ways=%d total TLB=%d\n",
469 c->tlbsizevtlb, c->tlbsizeftlbsets, c->tlbsizeftlbways, c->tlbsize);
470 }
471 #else
472 switch (config4 & MIPS_CONF4_MMUEXTDEF) {
473 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
474 c->tlbsize =
475 ((((config4 & MIPS_CONF4_MMUSIZEEXT) >>
476 MIPS_CONF4_MMUSIZEEXT_SHIFT) <<
477 MIPS_CONF1_TLBS_SIZE) |
478 (c->tlbsize - 1)) + 1;
479 c->tlbsizevtlb = c->tlbsize;
480 printk("MMUSizeExt found, total TLB=%d\n",c->tlbsize);
481 break;
482 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
483 c->tlbsizevtlb = ((c->tlbsizevtlb - 1) |
484 (((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
485 MIPS_CONF4_VTLBSIZEEXT_SHIFT) <<
486 MIPS_CONF1_TLBS_SIZE)) + 1;
487 c->tlbsize = c->tlbsizevtlb;
488 /* fall through */
489 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
490 newcf4 = (config4 & ~MIPS_CONF4_FTLBPAGESIZE) |
491 ((((fls(PAGE_SIZE >> BASIC_PAGE_SHIFT)-1)/2)+1) <<
492 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
493 write_c0_config4(newcf4);
494 back_to_back_c0_hazard();
495 config4 = read_c0_config4();
496 if (config4 != newcf4) {
497 printk(KERN_ERR "PAGE_SIZE 0x%0lx is not supported by FTLB (config4=0x%0x)\n",
498 PAGE_SIZE, config4);
499 if (conf6available && (cpu_capability & MIPS_FTLB_CAPABLE)) {
500 printk("Switching FTLB OFF\n");
501 config6 = read_c0_config6();
502 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
503 }
504 printk("Total TLB(VTLB) inuse: %d\n",c->tlbsizevtlb);
505 break;
506 }
507 c->tlbsizeftlbsets = 1 <<
508 ((config4 & MIPS_CONF4_FTLBSETS) >>
509 MIPS_CONF4_FTLBSETS_SHIFT);
510 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
511 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
512 c->tlbsize += (c->tlbsizeftlbways *
513 c->tlbsizeftlbsets);
514 printk("V/FTLB found: VTLB=%d, FTLB sets=%d, ways=%d total TLB=%d\n",
515 c->tlbsizevtlb, c->tlbsizeftlbsets, c->tlbsizeftlbways, c->tlbsize);
516 break;
517 }
518 #endif
519 }
520
521 c->kscratch_mask = (config4 >> 16) & 0xff;
522
523 return config4 & MIPS_CONF_M;
524 }
525
decode_config5(struct cpuinfo_mips * c)526 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
527 {
528 unsigned int config5;
529
530 config5 = read_c0_config5();
531 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
532 write_c0_config5(config5);
533
534 if (config5 & MIPS_CONF5_EVA)
535 c->options |= MIPS_CPU_EVA;
536 if (config5 & MIPS_CONF5_MRP)
537 c->options2 |= MIPS_CPU_MAAR;
538 if (config5 & MIPS_CONF5_L2C)
539 c->options2 |= MIPS_CPU_L2C;
540 if (config5 & MIPS_CONF5_VC)
541 c->options2 |= MIPS_CPU_VC;
542
543 return config5 & MIPS_CONF_M;
544 }
545
decode_config6_ftlb(struct cpuinfo_mips * c)546 static inline unsigned int decode_config6_ftlb(struct cpuinfo_mips *c)
547 {
548 unsigned int config6;
549
550 if (cpu_capability & MIPS_FTLB_CAPABLE) {
551
552 /*
553 * Can't rely on mips_ftlb_disabled since kernel command line
554 * hasn't been processed yet. Need to peek at the raw command
555 * line for "noftlb".
556 */
557 if (strstr(arcs_cmdline, "noftlb") == NULL) {
558 config6 = read_c0_config6();
559
560 printk("Enable FTLB attempt\n");
561 write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
562 back_to_back_c0_hazard();
563
564 return(1);
565 }
566 }
567
568 return(0);
569 }
570
571
decode_configs(struct cpuinfo_mips * c)572 static void decode_configs(struct cpuinfo_mips *c)
573 {
574 int ok, ok3 = 0, ok6 = 0;
575
576 /* MIPS32 or MIPS64 compliant CPU. */
577 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
578 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
579
580 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
581
582 ok = decode_config0(c); /* Read Config registers. */
583 BUG_ON(!ok); /* Arch spec violation! */
584 if (ok)
585 ok = decode_config1(c);
586 if (ok)
587 ok = decode_config2(c);
588 if (ok)
589 ok = ok3 = decode_config3(c);
590 if (ok)
591 ok = decode_config4(c,0,0); /* first pass - just return Mbit */
592 if (ok)
593 ok = decode_config5(c);
594 if (cpu_capability & MIPS_FTLB_CAPABLE)
595 ok6 = decode_config6_ftlb(c);
596
597 if (ok3)
598 ok = decode_config4(c,1,ok6); /* real parse pass, thanks HW team :-/ */
599
600 mips_probe_watch_registers(c);
601
602 if (cpu_has_mips_r2 || cpu_has_mips_r6)
603 c->core = read_c0_ebase() & 0x3ff;
604
605 if (cpu_has_rixi) {
606 write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);
607 back_to_back_c0_hazard();
608 if (read_c0_pagegrain() & PG_IEC) {
609 c->options |= MIPS_CPU_RIXI_EXCEPT;
610 pr_info("TLBRI/TLBXI exceptions are used\n");
611 }
612 }
613 }
614
615 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
616 | MIPS_CPU_COUNTER)
617
cpu_probe_legacy(struct cpuinfo_mips * c,unsigned int cpu)618 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
619 {
620 switch (c->processor_id & 0xff00) {
621 case PRID_IMP_R2000:
622 c->cputype = CPU_R2000;
623 __cpu_name[cpu] = "R2000";
624 set_isa(c, MIPS_CPU_ISA_I);
625 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
626 MIPS_CPU_NOFPUEX;
627 if (__cpu_has_fpu())
628 c->options |= MIPS_CPU_FPU;
629 c->tlbsize = 64;
630 break;
631 case PRID_IMP_R3000:
632 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
633 if (cpu_has_confreg()) {
634 c->cputype = CPU_R3081E;
635 __cpu_name[cpu] = "R3081";
636 } else {
637 c->cputype = CPU_R3000A;
638 __cpu_name[cpu] = "R3000A";
639 }
640 } else {
641 c->cputype = CPU_R3000;
642 __cpu_name[cpu] = "R3000";
643 }
644 set_isa(c, MIPS_CPU_ISA_I);
645 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
646 MIPS_CPU_NOFPUEX;
647 if (__cpu_has_fpu())
648 c->options |= MIPS_CPU_FPU;
649 c->tlbsize = 64;
650 break;
651 case PRID_IMP_R4000:
652 if (read_c0_config() & CONF_SC) {
653 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
654 c->cputype = CPU_R4400PC;
655 __cpu_name[cpu] = "R4400PC";
656 } else {
657 c->cputype = CPU_R4000PC;
658 __cpu_name[cpu] = "R4000PC";
659 }
660 } else {
661 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
662 c->cputype = CPU_R4400SC;
663 __cpu_name[cpu] = "R4400SC";
664 } else {
665 c->cputype = CPU_R4000SC;
666 __cpu_name[cpu] = "R4000SC";
667 }
668 }
669
670 set_isa(c, MIPS_CPU_ISA_III);
671 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
672 MIPS_CPU_WATCH | MIPS_CPU_VCE |
673 MIPS_CPU_LLSC;
674 c->tlbsize = 48;
675 break;
676 case PRID_IMP_VR41XX:
677 set_isa(c, MIPS_CPU_ISA_III);
678 c->options = R4K_OPTS;
679 c->tlbsize = 32;
680 switch (c->processor_id & 0xf0) {
681 case PRID_REV_VR4111:
682 c->cputype = CPU_VR4111;
683 __cpu_name[cpu] = "NEC VR4111";
684 break;
685 case PRID_REV_VR4121:
686 c->cputype = CPU_VR4121;
687 __cpu_name[cpu] = "NEC VR4121";
688 break;
689 case PRID_REV_VR4122:
690 if ((c->processor_id & 0xf) < 0x3) {
691 c->cputype = CPU_VR4122;
692 __cpu_name[cpu] = "NEC VR4122";
693 } else {
694 c->cputype = CPU_VR4181A;
695 __cpu_name[cpu] = "NEC VR4181A";
696 }
697 break;
698 case PRID_REV_VR4130:
699 if ((c->processor_id & 0xf) < 0x4) {
700 c->cputype = CPU_VR4131;
701 __cpu_name[cpu] = "NEC VR4131";
702 } else {
703 c->cputype = CPU_VR4133;
704 c->options |= MIPS_CPU_LLSC;
705 __cpu_name[cpu] = "NEC VR4133";
706 }
707 break;
708 default:
709 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
710 c->cputype = CPU_VR41XX;
711 __cpu_name[cpu] = "NEC Vr41xx";
712 break;
713 }
714 break;
715 case PRID_IMP_R4300:
716 c->cputype = CPU_R4300;
717 __cpu_name[cpu] = "R4300";
718 set_isa(c, MIPS_CPU_ISA_III);
719 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
720 MIPS_CPU_LLSC;
721 c->tlbsize = 32;
722 break;
723 case PRID_IMP_R4600:
724 c->cputype = CPU_R4600;
725 __cpu_name[cpu] = "R4600";
726 set_isa(c, MIPS_CPU_ISA_III);
727 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
728 MIPS_CPU_LLSC;
729 c->tlbsize = 48;
730 break;
731 #if 0
732 case PRID_IMP_R4650:
733 /*
734 * This processor doesn't have an MMU, so it's not
735 * "real easy" to run Linux on it. It is left purely
736 * for documentation. Commented out because it shares
737 * it's c0_prid id number with the TX3900.
738 */
739 c->cputype = CPU_R4650;
740 __cpu_name[cpu] = "R4650";
741 set_isa(c, MIPS_CPU_ISA_III);
742 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
743 c->tlbsize = 48;
744 break;
745 #endif
746 case PRID_IMP_TX39:
747 set_isa(c, MIPS_CPU_ISA_I);
748 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
749
750 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
751 c->cputype = CPU_TX3927;
752 __cpu_name[cpu] = "TX3927";
753 c->tlbsize = 64;
754 } else {
755 switch (c->processor_id & 0xff) {
756 case PRID_REV_TX3912:
757 c->cputype = CPU_TX3912;
758 __cpu_name[cpu] = "TX3912";
759 c->tlbsize = 32;
760 break;
761 case PRID_REV_TX3922:
762 c->cputype = CPU_TX3922;
763 __cpu_name[cpu] = "TX3922";
764 c->tlbsize = 64;
765 break;
766 }
767 }
768 break;
769 case PRID_IMP_R4700:
770 c->cputype = CPU_R4700;
771 __cpu_name[cpu] = "R4700";
772 set_isa(c, MIPS_CPU_ISA_III);
773 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
774 MIPS_CPU_LLSC;
775 c->tlbsize = 48;
776 break;
777 case PRID_IMP_TX49:
778 c->cputype = CPU_TX49XX;
779 __cpu_name[cpu] = "R49XX";
780 set_isa(c, MIPS_CPU_ISA_III);
781 c->options = R4K_OPTS | MIPS_CPU_LLSC;
782 if (!(c->processor_id & 0x08))
783 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
784 c->tlbsize = 48;
785 break;
786 case PRID_IMP_R5000:
787 c->cputype = CPU_R5000;
788 __cpu_name[cpu] = "R5000";
789 set_isa(c, MIPS_CPU_ISA_IV);
790 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
791 MIPS_CPU_LLSC;
792 c->tlbsize = 48;
793 break;
794 case PRID_IMP_R5432:
795 c->cputype = CPU_R5432;
796 __cpu_name[cpu] = "R5432";
797 set_isa(c, MIPS_CPU_ISA_IV);
798 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
799 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
800 c->tlbsize = 48;
801 break;
802 case PRID_IMP_R5500:
803 c->cputype = CPU_R5500;
804 __cpu_name[cpu] = "R5500";
805 set_isa(c, MIPS_CPU_ISA_IV);
806 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
807 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
808 c->tlbsize = 48;
809 break;
810 case PRID_IMP_NEVADA:
811 c->cputype = CPU_NEVADA;
812 __cpu_name[cpu] = "Nevada";
813 set_isa(c, MIPS_CPU_ISA_IV);
814 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
815 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
816 c->tlbsize = 48;
817 break;
818 case PRID_IMP_R6000:
819 c->cputype = CPU_R6000;
820 __cpu_name[cpu] = "R6000";
821 set_isa(c, MIPS_CPU_ISA_II);
822 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
823 MIPS_CPU_LLSC;
824 c->tlbsize = 32;
825 break;
826 case PRID_IMP_R6000A:
827 c->cputype = CPU_R6000A;
828 __cpu_name[cpu] = "R6000A";
829 set_isa(c, MIPS_CPU_ISA_II);
830 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
831 MIPS_CPU_LLSC;
832 c->tlbsize = 32;
833 break;
834 case PRID_IMP_RM7000:
835 c->cputype = CPU_RM7000;
836 __cpu_name[cpu] = "RM7000";
837 set_isa(c, MIPS_CPU_ISA_IV);
838 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
839 MIPS_CPU_LLSC;
840 /*
841 * Undocumented RM7000: Bit 29 in the info register of
842 * the RM7000 v2.0 indicates if the TLB has 48 or 64
843 * entries.
844 *
845 * 29 1 => 64 entry JTLB
846 * 0 => 48 entry JTLB
847 */
848 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
849 break;
850 case PRID_IMP_RM9000:
851 c->cputype = CPU_RM9000;
852 __cpu_name[cpu] = "RM9000";
853 set_isa(c, MIPS_CPU_ISA_IV);
854 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
855 MIPS_CPU_LLSC;
856 /*
857 * Bit 29 in the info register of the RM9000
858 * indicates if the TLB has 48 or 64 entries.
859 *
860 * 29 1 => 64 entry JTLB
861 * 0 => 48 entry JTLB
862 */
863 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
864 break;
865 case PRID_IMP_R8000:
866 c->cputype = CPU_R8000;
867 __cpu_name[cpu] = "RM8000";
868 set_isa(c, MIPS_CPU_ISA_IV);
869 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
870 MIPS_CPU_FPU | MIPS_CPU_32FPR |
871 MIPS_CPU_LLSC;
872 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
873 break;
874 case PRID_IMP_R10000:
875 c->cputype = CPU_R10000;
876 __cpu_name[cpu] = "R10000";
877 set_isa(c, MIPS_CPU_ISA_IV);
878 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
879 MIPS_CPU_FPU | MIPS_CPU_32FPR |
880 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
881 MIPS_CPU_LLSC;
882 c->tlbsize = 64;
883 break;
884 case PRID_IMP_R12000:
885 c->cputype = CPU_R12000;
886 __cpu_name[cpu] = "R12000";
887 set_isa(c, MIPS_CPU_ISA_IV);
888 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
889 MIPS_CPU_FPU | MIPS_CPU_32FPR |
890 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
891 MIPS_CPU_LLSC;
892 c->tlbsize = 64;
893 break;
894 case PRID_IMP_R14000:
895 c->cputype = CPU_R14000;
896 __cpu_name[cpu] = "R14000";
897 set_isa(c, MIPS_CPU_ISA_IV);
898 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
899 MIPS_CPU_FPU | MIPS_CPU_32FPR |
900 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
901 MIPS_CPU_LLSC;
902 c->tlbsize = 64;
903 break;
904 case PRID_IMP_LOONGSON2:
905 c->cputype = CPU_LOONGSON2;
906 __cpu_name[cpu] = "ICT Loongson-2";
907
908 switch (c->processor_id & PRID_REV_MASK) {
909 case PRID_REV_LOONGSON2E:
910 set_elf_platform(cpu, "loongson2e");
911 break;
912 case PRID_REV_LOONGSON2F:
913 set_elf_platform(cpu, "loongson2f");
914 break;
915 }
916
917 set_isa(c, MIPS_CPU_ISA_III);
918 c->options = R4K_OPTS |
919 MIPS_CPU_FPU | MIPS_CPU_LLSC |
920 MIPS_CPU_32FPR;
921 c->tlbsize = 64;
922 break;
923 case PRID_IMP_LOONGSON1:
924 decode_configs(c);
925
926 c->cputype = CPU_LOONGSON1;
927
928 switch (c->processor_id & PRID_REV_MASK) {
929 case PRID_REV_LOONGSON1B:
930 __cpu_name[cpu] = "Loongson 1B";
931 break;
932 }
933
934 break;
935 }
936 }
937
cpu_probe_mips(struct cpuinfo_mips * c,unsigned int cpu)938 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
939 {
940 switch (c->processor_id & 0xff00) {
941 case PRID_IMP_QEMU:
942 c->cputype = CPU_QEMU;
943 __cpu_name[cpu] = "MIPS GENERIC QEMU";
944 break;
945 case PRID_IMP_4KC:
946 c->cputype = CPU_4KC;
947 __cpu_name[cpu] = "MIPS 4Kc";
948 break;
949 case PRID_IMP_4KEC:
950 case PRID_IMP_4KECR2:
951 c->cputype = CPU_4KEC;
952 __cpu_name[cpu] = "MIPS 4KEc";
953 break;
954 case PRID_IMP_4KSC:
955 case PRID_IMP_4KSD:
956 c->cputype = CPU_4KSC;
957 __cpu_name[cpu] = "MIPS 4KSc";
958 break;
959 case PRID_IMP_5KC:
960 c->cputype = CPU_5KC;
961 __cpu_name[cpu] = "MIPS 5Kc";
962 break;
963 case PRID_IMP_5KE:
964 c->cputype = CPU_5KE;
965 __cpu_name[cpu] = "MIPS 5KE";
966 break;
967 case PRID_IMP_20KC:
968 c->cputype = CPU_20KC;
969 __cpu_name[cpu] = "MIPS 20Kc";
970 break;
971 case PRID_IMP_24K:
972 c->cputype = CPU_24K;
973 __cpu_name[cpu] = "MIPS 24Kc";
974 break;
975 case PRID_IMP_24KE:
976 c->cputype = CPU_24K;
977 __cpu_name[cpu] = "MIPS 24KEc";
978 break;
979 case PRID_IMP_25KF:
980 c->cputype = CPU_25KF;
981 __cpu_name[cpu] = "MIPS 25Kc";
982 break;
983 case PRID_IMP_34K:
984 c->cputype = CPU_34K;
985 __cpu_name[cpu] = "MIPS 34Kc";
986 break;
987 case PRID_IMP_74K:
988 c->cputype = CPU_74K;
989 __cpu_name[cpu] = "MIPS 74Kc";
990 break;
991 case PRID_IMP_M14KC:
992 c->cputype = CPU_M14KC;
993 __cpu_name[cpu] = "MIPS M14Kc";
994 break;
995 case PRID_IMP_M14KEC:
996 c->cputype = CPU_M14KEC;
997 __cpu_name[cpu] = "MIPS M14KEc";
998 break;
999 case PRID_IMP_1004K:
1000 c->cputype = CPU_1004K;
1001 __cpu_name[cpu] = "MIPS 1004Kc";
1002 break;
1003 case PRID_IMP_1074K:
1004 c->cputype = CPU_74K;
1005 __cpu_name[cpu] = "MIPS 1074Kc";
1006 break;
1007 case PRID_IMP_PROAPTIV_UP:
1008 c->cputype = CPU_PROAPTIV;
1009 __cpu_name[cpu] = "MIPS proAptiv";
1010 cpu_capability = MIPS_FTLB_CAPABLE;
1011 break;
1012 case PRID_IMP_PROAPTIV_MP:
1013 c->cputype = CPU_PROAPTIV;
1014 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1015 cpu_capability = MIPS_FTLB_CAPABLE;
1016 break;
1017 case PRID_IMP_INTERAPTIV_UP:
1018 c->cputype = CPU_INTERAPTIV;
1019 __cpu_name[cpu] = "MIPS interAptiv UP";
1020 break;
1021 case PRID_IMP_INTERAPTIV_MP:
1022 c->cputype = CPU_INTERAPTIV;
1023 __cpu_name[cpu] = "MIPS interAptiv";
1024 case PRID_IMP_VIRTUOSO:
1025 c->cputype = CPU_VIRTUOSO;
1026 __cpu_name[cpu] = "MIPS Virtuoso";
1027 break;
1028 case PRID_IMP_P5600:
1029 c->cputype = CPU_P5600;
1030 __cpu_name[cpu] = "MIPS P5600";
1031 cpu_capability = MIPS_FTLB_CAPABLE;
1032 break;
1033 case PRID_IMP_SAMURAI_UP:
1034 c->cputype = CPU_SAMURAI;
1035 __cpu_name[cpu] = "MIPS Samurai UP";
1036 break;
1037 }
1038 report_kernel();
1039 decode_configs(c);
1040
1041 spram_config();
1042 }
1043
cpu_probe_alchemy(struct cpuinfo_mips * c,unsigned int cpu)1044 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1045 {
1046 decode_configs(c);
1047 switch (c->processor_id & 0xff00) {
1048 case PRID_IMP_AU1_REV1:
1049 case PRID_IMP_AU1_REV2:
1050 c->cputype = CPU_ALCHEMY;
1051 switch ((c->processor_id >> 24) & 0xff) {
1052 case 0:
1053 __cpu_name[cpu] = "Au1000";
1054 break;
1055 case 1:
1056 __cpu_name[cpu] = "Au1500";
1057 break;
1058 case 2:
1059 __cpu_name[cpu] = "Au1100";
1060 break;
1061 case 3:
1062 __cpu_name[cpu] = "Au1550";
1063 break;
1064 case 4:
1065 __cpu_name[cpu] = "Au1200";
1066 if ((c->processor_id & 0xff) == 2)
1067 __cpu_name[cpu] = "Au1250";
1068 break;
1069 case 5:
1070 __cpu_name[cpu] = "Au1210";
1071 break;
1072 default:
1073 __cpu_name[cpu] = "Au1xxx";
1074 break;
1075 }
1076 break;
1077 }
1078 }
1079
cpu_probe_sibyte(struct cpuinfo_mips * c,unsigned int cpu)1080 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1081 {
1082 decode_configs(c);
1083
1084 switch (c->processor_id & 0xff00) {
1085 case PRID_IMP_SB1:
1086 c->cputype = CPU_SB1;
1087 __cpu_name[cpu] = "SiByte SB1";
1088 /* FPU in pass1 is known to have issues. */
1089 if ((c->processor_id & 0xff) < 0x02)
1090 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1091 break;
1092 case PRID_IMP_SB1A:
1093 c->cputype = CPU_SB1A;
1094 __cpu_name[cpu] = "SiByte SB1A";
1095 break;
1096 }
1097 }
1098
cpu_probe_sandcraft(struct cpuinfo_mips * c,unsigned int cpu)1099 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1100 {
1101 decode_configs(c);
1102 switch (c->processor_id & 0xff00) {
1103 case PRID_IMP_SR71000:
1104 c->cputype = CPU_SR71000;
1105 __cpu_name[cpu] = "Sandcraft SR71000";
1106 c->scache.ways = 8;
1107 c->tlbsize = 64;
1108 break;
1109 }
1110 }
1111
cpu_probe_nxp(struct cpuinfo_mips * c,unsigned int cpu)1112 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1113 {
1114 decode_configs(c);
1115 switch (c->processor_id & 0xff00) {
1116 case PRID_IMP_PR4450:
1117 c->cputype = CPU_PR4450;
1118 __cpu_name[cpu] = "Philips PR4450";
1119 set_isa(c, MIPS_CPU_ISA_M32R1);
1120 break;
1121 }
1122 }
1123
cpu_probe_broadcom(struct cpuinfo_mips * c,unsigned int cpu)1124 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1125 {
1126 decode_configs(c);
1127 switch (c->processor_id & 0xff00) {
1128 case PRID_IMP_BMIPS32_REV4:
1129 case PRID_IMP_BMIPS32_REV8:
1130 c->cputype = CPU_BMIPS32;
1131 __cpu_name[cpu] = "Broadcom BMIPS32";
1132 set_elf_platform(cpu, "bmips32");
1133 break;
1134 case PRID_IMP_BMIPS3300:
1135 case PRID_IMP_BMIPS3300_ALT:
1136 case PRID_IMP_BMIPS3300_BUG:
1137 c->cputype = CPU_BMIPS3300;
1138 __cpu_name[cpu] = "Broadcom BMIPS3300";
1139 set_elf_platform(cpu, "bmips3300");
1140 break;
1141 case PRID_IMP_BMIPS43XX: {
1142 int rev = c->processor_id & 0xff;
1143
1144 if (rev >= PRID_REV_BMIPS4380_LO &&
1145 rev <= PRID_REV_BMIPS4380_HI) {
1146 c->cputype = CPU_BMIPS4380;
1147 __cpu_name[cpu] = "Broadcom BMIPS4380";
1148 set_elf_platform(cpu, "bmips4380");
1149 } else {
1150 c->cputype = CPU_BMIPS4350;
1151 __cpu_name[cpu] = "Broadcom BMIPS4350";
1152 set_elf_platform(cpu, "bmips4350");
1153 }
1154 break;
1155 }
1156 case PRID_IMP_BMIPS5000:
1157 c->cputype = CPU_BMIPS5000;
1158 __cpu_name[cpu] = "Broadcom BMIPS5000";
1159 set_elf_platform(cpu, "bmips5000");
1160 c->options |= MIPS_CPU_ULRI;
1161 break;
1162 }
1163 }
1164
cpu_probe_cavium(struct cpuinfo_mips * c,unsigned int cpu)1165 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1166 {
1167 decode_configs(c);
1168 switch (c->processor_id & 0xff00) {
1169 case PRID_IMP_CAVIUM_CN38XX:
1170 case PRID_IMP_CAVIUM_CN31XX:
1171 case PRID_IMP_CAVIUM_CN30XX:
1172 c->cputype = CPU_CAVIUM_OCTEON;
1173 __cpu_name[cpu] = "Cavium Octeon";
1174 goto platform;
1175 case PRID_IMP_CAVIUM_CN58XX:
1176 case PRID_IMP_CAVIUM_CN56XX:
1177 case PRID_IMP_CAVIUM_CN50XX:
1178 case PRID_IMP_CAVIUM_CN52XX:
1179 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1180 __cpu_name[cpu] = "Cavium Octeon+";
1181 platform:
1182 set_elf_platform(cpu, "octeon");
1183 break;
1184 case PRID_IMP_CAVIUM_CN61XX:
1185 case PRID_IMP_CAVIUM_CN63XX:
1186 case PRID_IMP_CAVIUM_CN66XX:
1187 case PRID_IMP_CAVIUM_CN68XX:
1188 c->cputype = CPU_CAVIUM_OCTEON2;
1189 __cpu_name[cpu] = "Cavium Octeon II";
1190 set_elf_platform(cpu, "octeon2");
1191 break;
1192 default:
1193 printk(KERN_INFO "Unknown Octeon chip!\n");
1194 c->cputype = CPU_UNKNOWN;
1195 break;
1196 }
1197 }
1198
cpu_probe_ingenic(struct cpuinfo_mips * c,unsigned int cpu)1199 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1200 {
1201 decode_configs(c);
1202 /* JZRISC does not implement the CP0 counter. */
1203 c->options &= ~MIPS_CPU_COUNTER;
1204 switch (c->processor_id & 0xff00) {
1205 case PRID_IMP_JZRISC:
1206 c->cputype = CPU_JZRISC;
1207 __cpu_name[cpu] = "Ingenic JZRISC";
1208 break;
1209 default:
1210 panic("Unknown Ingenic Processor ID!");
1211 break;
1212 }
1213 }
1214
cpu_probe_netlogic(struct cpuinfo_mips * c,int cpu)1215 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1216 {
1217 decode_configs(c);
1218
1219 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
1220 c->cputype = CPU_ALCHEMY;
1221 __cpu_name[cpu] = "Au1300";
1222 /* following stuff is not for Alchemy */
1223 return;
1224 }
1225
1226 c->options = (MIPS_CPU_TLB |
1227 MIPS_CPU_4KEX |
1228 MIPS_CPU_COUNTER |
1229 MIPS_CPU_DIVEC |
1230 MIPS_CPU_WATCH |
1231 MIPS_CPU_EJTAG |
1232 MIPS_CPU_LLSC);
1233
1234 switch (c->processor_id & 0xff00) {
1235 case PRID_IMP_NETLOGIC_XLP8XX:
1236 case PRID_IMP_NETLOGIC_XLP3XX:
1237 c->cputype = CPU_XLP;
1238 __cpu_name[cpu] = "Netlogic XLP";
1239 break;
1240
1241 case PRID_IMP_NETLOGIC_XLR732:
1242 case PRID_IMP_NETLOGIC_XLR716:
1243 case PRID_IMP_NETLOGIC_XLR532:
1244 case PRID_IMP_NETLOGIC_XLR308:
1245 case PRID_IMP_NETLOGIC_XLR532C:
1246 case PRID_IMP_NETLOGIC_XLR516C:
1247 case PRID_IMP_NETLOGIC_XLR508C:
1248 case PRID_IMP_NETLOGIC_XLR308C:
1249 c->cputype = CPU_XLR;
1250 __cpu_name[cpu] = "Netlogic XLR";
1251 break;
1252
1253 case PRID_IMP_NETLOGIC_XLS608:
1254 case PRID_IMP_NETLOGIC_XLS408:
1255 case PRID_IMP_NETLOGIC_XLS404:
1256 case PRID_IMP_NETLOGIC_XLS208:
1257 case PRID_IMP_NETLOGIC_XLS204:
1258 case PRID_IMP_NETLOGIC_XLS108:
1259 case PRID_IMP_NETLOGIC_XLS104:
1260 case PRID_IMP_NETLOGIC_XLS616B:
1261 case PRID_IMP_NETLOGIC_XLS608B:
1262 case PRID_IMP_NETLOGIC_XLS416B:
1263 case PRID_IMP_NETLOGIC_XLS412B:
1264 case PRID_IMP_NETLOGIC_XLS408B:
1265 case PRID_IMP_NETLOGIC_XLS404B:
1266 c->cputype = CPU_XLR;
1267 __cpu_name[cpu] = "Netlogic XLS";
1268 break;
1269
1270 default:
1271 pr_info("Unknown Netlogic chip id [%02x]!\n",
1272 c->processor_id);
1273 c->cputype = CPU_XLR;
1274 break;
1275 }
1276
1277 if (c->cputype == CPU_XLP) {
1278 set_isa(c, MIPS_CPU_ISA_M64R2);
1279 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1280 /* This will be updated again after all threads are woken up */
1281 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1282 } else {
1283 set_isa(c, MIPS_CPU_ISA_M64R1);
1284 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1285 }
1286 }
1287
1288 #ifdef CONFIG_64BIT
1289 /* For use by uaccess.h */
1290 u64 __ua_limit;
1291 EXPORT_SYMBOL(__ua_limit);
1292 #endif
1293
1294 const char *__cpu_name[NR_CPUS];
1295 const char *__elf_platform;
1296 unsigned int fpu_fcr31 __read_mostly = 0;
1297 unsigned int system_has_fpu __read_mostly = 0;
1298 unsigned int global_fpu_id __read_mostly = 0;
1299
cpu_probe(void)1300 __cpuinit void cpu_probe(void)
1301 {
1302 struct cpuinfo_mips *c = ¤t_cpu_data;
1303 unsigned int cpu = smp_processor_id();
1304
1305 c->processor_id = PRID_IMP_UNKNOWN;
1306 c->fpu_id = FPIR_IMP_NONE;
1307 c->cputype = CPU_UNKNOWN;
1308
1309 c->processor_id = read_c0_prid();
1310 switch (c->processor_id & 0xff0000) {
1311 case PRID_COMP_LEGACY:
1312 cpu_probe_legacy(c, cpu);
1313 break;
1314 case PRID_COMP_MIPS:
1315 cpu_probe_mips(c, cpu);
1316 break;
1317 case PRID_COMP_ALCHEMY:
1318 cpu_probe_alchemy(c, cpu);
1319 break;
1320 case PRID_COMP_SIBYTE:
1321 cpu_probe_sibyte(c, cpu);
1322 break;
1323 case PRID_COMP_BROADCOM:
1324 cpu_probe_broadcom(c, cpu);
1325 break;
1326 case PRID_COMP_SANDCRAFT:
1327 cpu_probe_sandcraft(c, cpu);
1328 break;
1329 case PRID_COMP_NXP:
1330 cpu_probe_nxp(c, cpu);
1331 break;
1332 case PRID_COMP_CAVIUM:
1333 cpu_probe_cavium(c, cpu);
1334 break;
1335 case PRID_COMP_INGENIC:
1336 cpu_probe_ingenic(c, cpu);
1337 break;
1338 case PRID_COMP_NETLOGIC:
1339 cpu_probe_netlogic(c, cpu);
1340 break;
1341 }
1342
1343 BUG_ON(!__cpu_name[cpu]);
1344 BUG_ON(c->cputype == CPU_UNKNOWN);
1345
1346 /*
1347 * Platform code can force the cpu type to optimize code
1348 * generation. In that case be sure the cpu type is correctly
1349 * manually setup otherwise it could trigger some nasty bugs.
1350 */
1351 BUG_ON(current_cpu_type() != c->cputype);
1352
1353 if (mips_fpu_disabled)
1354 c->options &= ~MIPS_CPU_FPU;
1355
1356 if (mips_dsp_disabled)
1357 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1358
1359 c->htw_level = 0;
1360 if (c->options2 & MIPS_CPU_HTW)
1361 write_c0_pwctl(HTW_PWCTL_BASE);
1362 if (mips_htw_disabled)
1363 c->options2 &= ~MIPS_CPU_HTW;
1364
1365 if (c->options & MIPS_CPU_FPU) {
1366 system_has_fpu = 1;
1367 fpu_fcr31 = cpu_test_fpu_csr31(FPU_CSR_DEFAULT);
1368
1369 global_fpu_id = cpu_get_fpu_id();
1370 c->fpu_id = global_fpu_id;
1371
1372 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
1373 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
1374 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
1375 if (c->fpu_id & MIPS_FPIR_3D)
1376 c->ases |= MIPS_ASE_MIPS3D;
1377 if (c->fpu_id & MIPS_FPIR_HAS2008)
1378 fpu_fcr31 = cpu_test_fpu_csr31(FPU_CSR_DEFAULT|FPU_CSR_MAC2008|FPU_CSR_ABS2008|FPU_CSR_NAN2008);
1379 if (c->fpu_id & MIPS_FPIR_FREP) {
1380 c->options2 |= MIPS_CPU_FRE;
1381 pr_info("FPU has FRE support\n");
1382 }
1383 }
1384 }
1385
1386 if (cpu_has_mips_r2 || cpu_has_mips_r6) {
1387 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1388 /* R2 has Performance Counter Interrupt indicator */
1389 c->options |= MIPS_CPU_PCI;
1390 }
1391 else
1392 c->srsets = 1;
1393
1394 if (cpu_has_msa) {
1395 c->msa_id = cpu_get_msa_id();
1396 WARN(c->msa_id & MSA_IR_WRPF,
1397 "Vector register partitioning unimplemented!");
1398 elf_hwcap |= HWCAP_MIPS_MSA;
1399 }
1400
1401 cpu_probe_vmbits(c);
1402 cpu_probe_pabits(c);
1403
1404 #ifdef CONFIG_64BIT
1405 if (cpu == 0)
1406 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1407 #endif
1408 }
1409
cpu_report(void)1410 __cpuinit void cpu_report(void)
1411 {
1412 struct cpuinfo_mips *c = ¤t_cpu_data;
1413
1414 printk(KERN_INFO "CPU%d revision is: %08x (%s)\n",
1415 smp_processor_id(), c->processor_id, cpu_name_string());
1416 if (c->options & MIPS_CPU_FPU)
1417 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1418 if (cpu_has_msa)
1419 pr_info("MSA revision is: %08x\n", c->msa_id);
1420 }
1421