| /arch/x86/kernel/apic/ |
| D | apic.c | 292 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); in native_apic_icr_write()
293 apic_write(APIC_ICR, low); in native_apic_icr_write()
366 apic_write(APIC_LVTT, lvtt_value); in __setup_APIC_LVTT()
384 apic_write(APIC_TDCR, in __setup_APIC_LVTT()
389 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); in __setup_APIC_LVTT()
476 apic_write(reg, new); in setup_APIC_eilvt()
488 apic_write(APIC_TMICT, delta); in lapic_next_event()
527 apic_write(APIC_LVTT, v); in lapic_timer_setup()
528 apic_write(APIC_TMICT, 0); in lapic_timer_setup()
1010 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); in clear_local_APIC()
[all …]
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| D | bigsmp_32.c | 63 apic_write(APIC_DFR, APIC_DFR_FLAT); in bigsmp_init_apic_ldr()
65 apic_write(APIC_LDR, val); in bigsmp_init_apic_ldr()
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| D | apic_flat_64.c | 50 apic_write(APIC_DFR, APIC_DFR_FLAT); in flat_init_apic_ldr()
53 apic_write(APIC_LDR, val); in flat_init_apic_ldr()
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| D | io_apic.c | 1812 apic_write(APIC_ESR, 0); in print_local_APIC()
2671 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); in mask_lapic_irq()
2679 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); in unmask_lapic_irq()
2802 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); in check_timer()
2888 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ in check_timer()
2897 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); in check_timer()
2905 apic_write(APIC_LVT0, APIC_DM_EXTINT); in check_timer()
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| D | x2apic_uv_x.c | 343 apic_write(APIC_SELF_IPI, vector); in uv_send_IPI_self()
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| /arch/x86/include/asm/ |
| D | x2apic.h | 46 apic_write(APIC_SELF_IPI, vector); in x2apic_send_IPI_self()
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| D | apic.h | 403 static inline void apic_write(u32 reg, u32 val) in apic_write() function
438 static inline void apic_write(u32 reg, u32 val) { } in apic_write() function
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| /arch/x86/kernel/cpu/mcheck/ |
| D | therm_throt.c | 497 apic_write(APIC_LVTTHMR, lvtthmr_init); in intel_init_thermal()
526 apic_write(APIC_LVTTHMR, h); in intel_init_thermal()
566 apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED); in intel_init_thermal()
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| D | mce_intel.c | 383 apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED); in intel_init_cmci()
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| /arch/x86/oprofile/ |
| D | nmi_int.c | 352 apic_write(APIC_LVTPC, APIC_DM_NMI); in nmi_cpu_setup()
384 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); in nmi_cpu_shutdown()
385 apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu)); in nmi_cpu_shutdown()
386 apic_write(APIC_LVTERR, v); in nmi_cpu_shutdown()
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| D | op_model_ppro.c | 145 apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED); in ppro_check_ctrs()
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| D | op_model_p4.c | 661 apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED); in p4_check_ctrs()
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| /arch/x86/kernel/ |
| D | smpboot.c | 510 apic_write(APIC_ESR, 0); in wakeup_secondary_cpu_via_nmi()
536 apic_write(APIC_ESR, 0); in wakeup_secondary_cpu_via_init()
594 apic_write(APIC_ESR, 0); in wakeup_secondary_cpu_via_init()
623 apic_write(APIC_ESR, 0); in wakeup_secondary_cpu_via_init()
804 apic_write(APIC_ESR, 0); in do_boot_cpu()
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| D | kvm.c | 333 apic_write(APIC_EOI, APIC_EOI_ACK); in kvm_guest_apic_eoi_write()
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| /arch/x86/platform/uv/ |
| D | uv_nmi.c | 700 apic_write(APIC_LVT1, value); in uv_nmi_init()
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| /arch/x86/kernel/cpu/ |
| D | perf_event.c | 1244 apic_write(APIC_LVTPC, APIC_DM_NMI); in x86_pmu_handle_irq()
1291 apic_write(APIC_LVTPC, APIC_DM_NMI); in perf_events_lapic_init()
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| D | perf_event_intel.c | 1359 apic_write(APIC_LVTPC, APIC_DM_NMI); in intel_pmu_handle_irq()
1443 apic_write(APIC_LVTPC, APIC_DM_NMI); in intel_pmu_handle_irq()
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| D | perf_event_p4.c | 1057 apic_write(APIC_LVTPC, APIC_DM_NMI); in p4_pmu_handle_irq()
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