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Searched refs:ccm (Results 1 – 17 of 17) sorted by relevance

/arch/arm/mach-imx/
Dclk-imx25.c57 #define ccm(x) (ccm_base + (x)) macro
99 clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL)); in __mx25_clocks_init()
100 clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL)); in __mx25_clocks_init()
102 …clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)… in __mx25_clocks_init()
103 clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2); in __mx25_clocks_init()
104 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
105 clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6); in __mx25_clocks_init()
107 …clk[per0_sel] = imx_clk_mux("per0_sel", ccm(CCM_MCR), 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)… in __mx25_clocks_init()
108 …clk[per1_sel] = imx_clk_mux("per1_sel", ccm(CCM_MCR), 1, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)… in __mx25_clocks_init()
109 …clk[per2_sel] = imx_clk_mux("per2_sel", ccm(CCM_MCR), 2, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)… in __mx25_clocks_init()
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Dclk-imx1.c38 static void __iomem *ccm __initdata;
39 #define CCM_CSCR (ccm + 0x0000)
40 #define CCM_MPCTL0 (ccm + 0x0004)
41 #define CCM_SPCTL0 (ccm + 0x000c)
42 #define CCM_PCDR (ccm + 0x0020)
43 #define SCM_GCCR (ccm + 0x0810)
78 ccm = MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR); in mx1_clocks_init()
108 ccm = of_iomap(np, 0); in mx1_clocks_init_dt()
109 BUG_ON(!ccm); in mx1_clocks_init_dt()
Dclk-imx21.c23 static void __iomem *ccm __initdata;
26 #define CCM_CSCR (ccm + 0x00)
27 #define CCM_MPCTL0 (ccm + 0x04)
28 #define CCM_SPCTL0 (ccm + 0x0c)
29 #define CCM_PCDR0 (ccm + 0x18)
30 #define CCM_PCDR1 (ccm + 0x1c)
31 #define CCM_PCCR0 (ccm + 0x20)
32 #define CCM_PCCR1 (ccm + 0x24)
44 BUG_ON(!ccm); in _mx21_clocks_init()
124 ccm = ioremap(MX21_CCM_BASE_ADDR, SZ_2K); in mx21_clocks_init()
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Dclk-imx27.c13 static void __iomem *ccm __initdata;
16 #define CCM_CSCR (ccm + 0x00)
17 #define CCM_MPCTL0 (ccm + 0x04)
18 #define CCM_MPCTL1 (ccm + 0x08)
19 #define CCM_SPCTL0 (ccm + 0x0c)
20 #define CCM_SPCTL1 (ccm + 0x10)
21 #define CCM_PCDR0 (ccm + 0x18)
22 #define CCM_PCDR1 (ccm + 0x1c)
23 #define CCM_PCCR0 (ccm + 0x20)
24 #define CCM_PCCR1 (ccm + 0x24)
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/arch/arm64/crypto/
DMakefile23 obj-$(CONFIG_CRYPTO_AES_ARM64_CE_CCM) += aes-ce-ccm.o
24 aes-ce-ccm-y := aes-ce-ccm-glue.o aes-ce-ccm-core.o
/arch/arm/boot/dts/
Dimx31.dtsi114 clks: ccm@53f80000{
115 compatible = "fsl,imx31-ccm";
Dimx1.dtsi189 clks: ccm@0021b000 {
190 compatible = "fsl,imx1-ccm";
Dimx35.dtsi190 clks: ccm@53f80000 {
191 compatible = "fsl,imx35-ccm";
Dimx50.dtsi331 clks: ccm@53fd4000{
332 compatible = "fsl,imx50-ccm";
Dvf610.dtsi337 clks: ccm@4006b000 {
338 compatible = "fsl,vf610-ccm";
Dimx25.dtsi307 clks: ccm@53f80000 {
308 compatible = "fsl,imx25-ccm";
Dimx27.dtsi519 clks: ccm@10027000{
520 compatible = "fsl,imx27-ccm";
Dimx51.dtsi417 clks: ccm@73fd4000{
418 compatible = "fsl,imx51-ccm";
Dimx53.dtsi523 clks: ccm@53fd4000{
524 compatible = "fsl,imx53-ccm";
Dimx6sl.dtsi430 clks: ccm@020c4000 {
431 compatible = "fsl,imx6sl-ccm";
Dimx6qdl.dtsi515 clks: ccm@020c4000 {
516 compatible = "fsl,imx6q-ccm";
Dimx6sx.dtsi528 clks: ccm@020c4000 {
529 compatible = "fsl,imx6sx-ccm";