| /arch/unicore32/kernel/ |
| D | clock.c | 32 unsigned long rate; member
38 .rate = CLOCK_TICK_RATE,
95 return clk->rate; in clk_get_rate()
100 unsigned long rate; member
104 {.rate = 25175000, .cfg = 0x00002001, .div = 0x9},
105 {.rate = 31500000, .cfg = 0x00002001, .div = 0x7},
106 {.rate = 40000000, .cfg = 0x00003801, .div = 0x9},
107 {.rate = 49500000, .cfg = 0x00003801, .div = 0x7},
108 {.rate = 65000000, .cfg = 0x00002c01, .div = 0x4},
109 {.rate = 78750000, .cfg = 0x00002400, .div = 0x7},
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| /arch/arm/mach-ep93xx/ |
| D | clock.c | 32 unsigned long rate; member
39 int (*set_rate)(struct clk *clk, unsigned long rate);
45 static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
46 static int set_div_rate(struct clk *clk, unsigned long rate);
47 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
48 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
51 .rate = EP93XX_EXT_CLK_RATE,
103 .rate = EP93XX_EXT_CLK_RATE,
107 .rate = EP93XX_EXT_CLK_RATE,
307 unsigned long rate = clk_get_rate(clk->parent); in get_uart_rate() local
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| /arch/c6x/platforms/ |
| D | pll.c | 81 return clk->rate; in clk_get_rate()
85 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
91 return clk->round_rate(clk, rate); in clk_round_rate()
93 return clk->rate; in clk_round_rate()
104 clk->rate = clk->recalc(clk); in propagate_rate()
109 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
118 ret = clk->set_rate(clk, rate); in clk_set_rate()
123 clk->rate = clk->recalc(clk); in clk_set_rate()
151 clk->rate = clk->recalc(clk); in clk_set_parent()
164 if (WARN(clk->parent && !clk->parent->rate, in clk_register()
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| /arch/blackfin/mach-bf609/ |
| D | clock.c | 115 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
119 ret = clk->ops->round_rate(clk, rate); in clk_round_rate()
124 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
128 ret = clk->ops->set_rate(clk, rate); in clk_set_rate()
135 return clk->rate; in vco_get_rate()
148 clk->parent->rate = clk_get_rate(clk->parent); in pll_get_rate()
149 return clk->parent->rate / (df + 1) * msel * 2; in pll_get_rate()
152 unsigned long pll_round_rate(struct clk *clk, unsigned long rate) in pll_round_rate() argument
155 div = rate / clk->parent->rate; in pll_round_rate()
156 return clk->parent->rate * div; in pll_round_rate()
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| /arch/arm/mach-omap2/ |
| D | sdram-nokia.c | 129 long rate; member
141 static unsigned long sdrc_get_fclk_period(long rate) in sdrc_get_fclk_period() argument
144 return 1000000000 / rate; in sdrc_get_fclk_period()
147 static unsigned int sdrc_ps_to_ticks(unsigned int time_ps, long rate) in sdrc_ps_to_ticks() argument
152 tick_ps = sdrc_get_fclk_period(rate); in sdrc_ps_to_ticks()
159 int ticks, long rate, const char *name) in set_sdrc_timing_regval() argument
175 (unsigned int)sdrc_get_fclk_period(rate) * ticks / in set_sdrc_timing_regval()
183 #define SDRC_SET_ONE(reg, st, end, field, rate) \ argument
185 memory_timings->field, (rate), #field) < 0) \
188 #define SDRC_SET_ONE(reg, st, end, field, rate) \ argument
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| D | sdram-qimonda-hyb18m512160af-6.h | 22 .rate = 166000000,
29 .rate = 165941176,
36 .rate = 83000000,
43 .rate = 82970588,
50 .rate = 0
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| D | sdram-hynix-h8mbx00u0mer-0em.h | 19 .rate = 200000000,
26 .rate = 166000000,
33 .rate = 100000000,
40 .rate = 83000000,
47 .rate = 0
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| D | sdram-numonyx-m65kxxxxam.h | 19 .rate = 200000000,
26 .rate = 166000000,
33 .rate = 133000000,
40 .rate = 83000000,
47 .rate = 0
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| D | sdram-micron-mt46h32m32lf-6.h | 23 .rate = 166000000,
30 .rate = 165941176,
37 .rate = 83000000,
44 .rate = 82970588,
51 .rate = 0
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| D | clkt34xx_dpll3m2.c | 47 int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate, in omap3_core_dpll_m2_set_rate() argument
60 if (!clk || !rate) in omap3_core_dpll_m2_set_rate()
63 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); in omap3_core_dpll_m2_set_rate()
64 if (validrate != rate) in omap3_core_dpll_m2_set_rate()
69 if (rate > clkrate) in omap3_core_dpll_m2_set_rate()
70 sdrcrate <<= ((rate / clkrate) >> 1); in omap3_core_dpll_m2_set_rate()
72 sdrcrate >>= ((clkrate / rate) >> 1); in omap3_core_dpll_m2_set_rate()
106 new_div, unlock_dll, c, rate > clkrate, in omap3_core_dpll_m2_set_rate()
113 new_div, unlock_dll, c, rate > clkrate, in omap3_core_dpll_m2_set_rate()
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| D | clkt2xxx_dpllcore.c | 111 int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, in omap2_reprogram_dpllcore() argument
123 if ((rate == (cur_rate / 2)) && (mult == 2)) { in omap2_reprogram_dpllcore()
125 } else if ((rate == (cur_rate * 2)) && (mult == 1)) { in omap2_reprogram_dpllcore()
127 } else if (rate != cur_rate) { in omap2_reprogram_dpllcore()
128 valid_rate = omap2_dpllcore_round_rate(rate); in omap2_reprogram_dpllcore()
129 if (valid_rate != rate) in omap2_reprogram_dpllcore()
147 if (rate > low) { in omap2_reprogram_dpllcore()
149 mult = ((rate / 2) / 1000000); in omap2_reprogram_dpllcore()
153 mult = (rate / 1000000); in omap2_reprogram_dpllcore()
162 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ in omap2_reprogram_dpllcore()
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| /arch/arm/plat-versatile/ |
| D | clock.c | 34 return clk->rate; in clk_get_rate()
38 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
42 ret = clk->ops->round(clk, rate); in clk_round_rate()
47 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
51 ret = clk->ops->set(clk, rate); in clk_set_rate()
56 long icst_clk_round(struct clk *clk, unsigned long rate) in icst_clk_round() argument
59 vco = icst_hz_to_vco(clk->params, rate); in icst_clk_round()
64 int icst_clk_set(struct clk *clk, unsigned long rate) in icst_clk_set() argument
68 vco = icst_hz_to_vco(clk->params, rate); in icst_clk_set()
69 clk->rate = icst_hz(clk->params, vco); in icst_clk_set()
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| /arch/sh/kernel/cpu/sh4/ |
| D | clock-sh4-202.c | 28 return clk->parent->rate / frqcr3_divisors[idx]; in emi_clk_recalc()
31 static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) in frqcr3_lookup() argument
33 int divisor = clk->parent->rate / rate; in frqcr3_lookup()
56 return clk->parent->rate / frqcr3_divisors[idx]; in femi_clk_recalc()
84 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) in shoc_clk_init()
94 return clk->parent->rate / frqcr3_divisors[idx]; in shoc_clk_recalc()
97 static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate) in shoc_clk_verify_rate() argument
104 if (rate > bclk_rate) in shoc_clk_verify_rate()
106 if (rate > 66000000) in shoc_clk_verify_rate()
112 static int shoc_clk_set_rate(struct clk *clk, unsigned long rate) in shoc_clk_set_rate() argument
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| /arch/arm/mach-omap1/ |
| D | clock.c | 57 return clk->parent->rate / div; in omap1_sossi_recalc()
135 static int calc_dsor_exp(struct clk *clk, unsigned long rate) in calc_dsor_exp() argument
156 realrate = parent->rate; in calc_dsor_exp()
158 if (realrate <= rate) in calc_dsor_exp()
172 return clk->parent->rate / dsor; in omap1_ckctl_recalc()
190 return clk->parent->rate / dsor; in omap1_ckctl_recalc_dsp_domain()
194 int omap1_select_table_rate(struct clk *clk, unsigned long rate) in omap1_select_table_rate() argument
200 ref_rate = ck_ref_p->rate; in omap1_select_table_rate()
202 for (ptr = omap1_rate_table; ptr->rate; ptr++) { in omap1_select_table_rate()
210 if (ptr->rate <= rate) in omap1_select_table_rate()
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| D | clock.h | 50 #define __clk_get_rate(clk) (clk->rate)
148 unsigned long rate; member
168 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
169 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
200 extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
201 extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
203 extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
206 extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
207 extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
209 extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
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| D | time.c | 167 static __init void omap_init_mpu_timer(unsigned long rate) in omap_init_mpu_timer() argument
170 omap_mpu_timer_start(0, (rate / HZ) - 1, 1); in omap_init_mpu_timer()
173 clockevents_config_and_register(&clockevent_mpu_timer1, rate, in omap_init_mpu_timer()
189 static void __init omap_init_clocksource(unsigned long rate) in omap_init_clocksource() argument
196 sched_clock_register(omap_mpu_read_sched_clock, 32, rate); in omap_init_clocksource()
198 if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate, in omap_init_clocksource()
206 unsigned long rate; in omap_mpu_timer_init() local
210 rate = clk_get_rate(ck_ref); in omap_mpu_timer_init()
214 rate /= 2; in omap_mpu_timer_init()
216 omap_init_mpu_timer(rate); in omap_mpu_timer_init()
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| /arch/arm/mach-imx/ |
| D | clk-pllv3.c | 110 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate, in clk_pllv3_round_rate() argument
115 return (rate >= parent_rate * 22) ? parent_rate * 22 : in clk_pllv3_round_rate()
119 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, in clk_pllv3_set_rate() argument
125 if (rate == parent_rate * 22) in clk_pllv3_set_rate()
127 else if (rate == parent_rate * 20) in clk_pllv3_set_rate()
157 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate, in clk_pllv3_sys_round_rate() argument
165 if (rate > max_rate) in clk_pllv3_sys_round_rate()
166 rate = max_rate; in clk_pllv3_sys_round_rate()
167 else if (rate < min_rate) in clk_pllv3_sys_round_rate()
168 rate = min_rate; in clk_pllv3_sys_round_rate()
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| /arch/arm/mach-davinci/ |
| D | clock.c | 129 return clk->rate; in clk_get_rate()
133 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
139 return clk->round_rate(clk, rate); in clk_round_rate()
141 return clk->rate; in clk_round_rate()
152 clk->rate = clk->recalc(clk); in propagate_rate()
157 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
166 ret = clk->set_rate(clk, rate); in clk_set_rate()
171 clk->rate = clk->recalc(clk); in clk_set_rate()
199 clk->rate = clk->recalc(clk); in clk_set_parent()
212 if (WARN(clk->parent && !clk->parent->rate, in clk_register()
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| /arch/mips/lantiq/ |
| D | clk.c | 34 cpu_clk_generic[0].rate = cpu; in clkdev_add_static()
35 cpu_clk_generic[1].rate = fpi; in clkdev_add_static()
36 cpu_clk_generic[2].rate = io; in clkdev_add_static()
37 cpu_clk_generic[3].rate = ppe; in clkdev_add_static()
72 if (clk->rate != 0) in clk_get_rate()
73 return clk->rate; in clk_get_rate()
82 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
89 while (*r && (*r != rate)) in clk_set_rate()
93 clk->cl.dev_id, clk->cl.con_id, rate); in clk_set_rate()
97 clk->rate = rate; in clk_set_rate()
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| /arch/mips/ar7/ |
| D | clock.c | 101 .rate = 125000000,
105 .rate = 150000000,
195 base_clock = cpu_clk.rate; in tnetd7300_get_clock()
222 int base_clock = bus_clk.rate; in tnetd7300_set_clock()
226 base_clock = bus_clk.rate; in tnetd7300_set_clock()
235 base_clock = cpu_clk.rate; in tnetd7300_set_clock()
257 bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT, in tnetd7300_init_clocks()
261 cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT, in tnetd7300_init_clocks()
264 cpu_clk.rate = bus_clk.rate; in tnetd7300_init_clocks()
266 if (dsp_clk.rate == 250000000) in tnetd7300_init_clocks()
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| /arch/mips/loongson/lemote-2f/ |
| D | clock.c | 47 .rate = 800000000,
83 return (unsigned long)clk->rate; in clk_get_rate()
92 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
94 unsigned int rate_khz = rate / 1000; in clk_set_rate()
103 ret = clk->ops->set_rate(clk, rate, 0); in clk_set_rate()
116 clk->rate = rate; in clk_set_rate()
126 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
132 rounded = clk->ops->round_rate(clk, rate); in clk_round_rate()
138 return rate; in clk_round_rate()
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| /arch/arm/mach-pxa/ |
| D | clock.c | 46 unsigned long rate; in clk_get_rate() local
48 rate = clk->rate; in clk_get_rate()
50 rate = clk->ops->getrate(clk); in clk_get_rate()
52 return rate; in clk_get_rate()
56 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
63 ret = clk->ops->setrate(clk, rate); in clk_set_rate()
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| /arch/arm/mach-lpc32xx/ |
| D | clock.c | 120 while (clk->rate == 0) in local_return_parent_rate()
123 return clk->rate; in local_return_parent_rate()
128 .rate = LPC32XX_CLOCK_OSC_FREQ,
193 .rate = LPC32XX_CLOCK_OSC_FREQ * 397,
199 .rate = LPC32XX_MAIN_OSC_FREQ,
262 clkin = clk_armpll.parent->rate; in local_update_armpll_rate()
265 clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg); in local_update_armpll_rate()
383 return clk_check_pll_setup(clk_usbpll.parent->rate, in local_clk_usbpll_setup()
452 unsigned long rate) in local_usbpll_round_rate() argument
461 rate = rate * 1000; in local_usbpll_round_rate()
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| /arch/arm/common/ |
| D | timer-sp.c | 38 long rate; in sp804_get_clock_rate() local
56 rate = clk_get_rate(clk); in sp804_get_clock_rate()
57 if (rate < 0) { in sp804_get_clock_rate()
58 pr_err("sp804: clock failed to get rate: %ld\n", rate); in sp804_get_clock_rate()
64 return rate; in sp804_get_clock_rate()
79 long rate; in __sp804_clocksource_and_sched_clock_init() local
90 rate = sp804_get_clock_rate(clk); in __sp804_clocksource_and_sched_clock_init()
92 if (rate < 0) in __sp804_clocksource_and_sched_clock_init()
103 rate, 200, 32, clocksource_mmio_readl_down); in __sp804_clocksource_and_sched_clock_init()
107 sched_clock_register(sp804_read, 32, rate); in __sp804_clocksource_and_sched_clock_init()
[all …]
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| /arch/arm/mach-mmp/ |
| D | clock.c | 81 unsigned long rate; in clk_get_rate() local
84 rate = clk->ops->getrate(clk); in clk_get_rate()
86 rate = clk->rate; in clk_get_rate()
88 return rate; in clk_get_rate()
92 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
99 ret = clk->ops->setrate(clk, rate); in clk_set_rate()
|