/arch/x86/oprofile/ |
D | op_model_amd.c | 143 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl); in op_amd_handle_ibs() 145 rdmsrl(MSR_AMD64_IBSFETCHLINAD, val); in op_amd_handle_ibs() 150 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val); in op_amd_handle_ibs() 162 rdmsrl(MSR_AMD64_IBSOPCTL, ctl); in op_amd_handle_ibs() 164 rdmsrl(MSR_AMD64_IBSOPRIP, val); in op_amd_handle_ibs() 168 rdmsrl(MSR_AMD64_IBSOPDATA, val); in op_amd_handle_ibs() 170 rdmsrl(MSR_AMD64_IBSOPDATA2, val); in op_amd_handle_ibs() 172 rdmsrl(MSR_AMD64_IBSOPDATA3, val); in op_amd_handle_ibs() 174 rdmsrl(MSR_AMD64_IBSDCLINAD, val); in op_amd_handle_ibs() 176 rdmsrl(MSR_AMD64_IBSDCPHYSAD, val); in op_amd_handle_ibs() [all …]
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D | op_model_ppro.c | 99 rdmsrl(msrs->controls[i].addr, val); in ppro_setup_ctrs() 116 rdmsrl(msrs->controls[i].addr, val); in ppro_setup_ctrs() 136 rdmsrl(msrs->counters[i].addr, val); in ppro_check_ctrs() 165 rdmsrl(msrs->controls[i].addr, val); in ppro_start() 181 rdmsrl(msrs->controls[i].addr, val); in ppro_stop()
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D | nmi_int.c | 83 rdmsrl(counters[i].addr, counters[i].saved); in nmi_cpu_save_registers() 88 rdmsrl(controls[i].addr, controls[i].saved); in nmi_cpu_save_registers() 209 rdmsrl(counters[i].addr, multiplex[virt].saved); in nmi_cpu_save_mpx_registers()
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/arch/x86/platform/olpc/ |
D | olpc-xo1-rtc.c | 70 rdmsrl(MSR_RTC_DOMA_OFFSET, rtc_info.rtc_day_alarm); in xo1_rtc_init() 71 rdmsrl(MSR_RTC_MONA_OFFSET, rtc_info.rtc_mon_alarm); in xo1_rtc_init() 72 rdmsrl(MSR_RTC_CEN_OFFSET, rtc_info.rtc_century); in xo1_rtc_init()
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/arch/x86/kernel/cpu/mcheck/ |
D | mce_intel.c | 80 rdmsrl(MSR_IA32_MCG_CAP, cap); in cmci_supported() 150 rdmsrl(MSR_IA32_MCx_CTL2(bank), val); in cmci_storm_disable_banks() 226 rdmsrl(MSR_IA32_MCx_CTL2(i), val); in cmci_discover() 250 rdmsrl(MSR_IA32_MCx_CTL2(i), val); in cmci_discover() 301 rdmsrl(MSR_IA32_MCx_CTL2(bank), val); in __cmci_disable_bank()
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D | therm_throt.c | 388 rdmsrl(MSR_IA32_THERM_STATUS, msr_val); in intel_thermal_interrupt() 404 rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val); in intel_thermal_interrupt()
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/arch/x86/power/ |
D | cpu.c | 95 rdmsrl(MSR_FS_BASE, ctxt->fs_base); in __save_processor_state() 96 rdmsrl(MSR_GS_BASE, ctxt->gs_base); in __save_processor_state() 97 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); in __save_processor_state() 100 rdmsrl(MSR_EFER, ctxt->efer); in __save_processor_state()
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/arch/x86/kernel/cpu/ |
D | mshyperv.c | 101 rdmsrl(HV_X64_MSR_TIME_REF_COUNT, current_tick); in read_hv_clock() 131 rdmsrl(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency); in ms_hyperv_init_platform()
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D | perf_event_intel_lbr.c | 141 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); in __intel_pmu_lbr_enable() 150 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); in __intel_pmu_lbr_disable() 244 rdmsrl(x86_pmu.lbr_tos, tos); in intel_pmu_lbr_tos() 265 rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr); in intel_pmu_lbr_read_32() 297 rdmsrl(x86_pmu.lbr_from + lbr_idx, from); in intel_pmu_lbr_read_64() 298 rdmsrl(x86_pmu.lbr_to + lbr_idx, to); in intel_pmu_lbr_read_64()
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D | perf_event_knc.c | 161 rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); in knc_pmu_disable_all() 170 rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); in knc_pmu_enable_all() 202 rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_STATUS, status); in knc_pmu_get_status()
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D | perf_event_p6.c | 142 rdmsrl(MSR_P6_EVNTSEL0, val); in p6_pmu_disable_all() 152 rdmsrl(MSR_P6_EVNTSEL0, val); in p6_pmu_enable_all()
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D | amd.c | 312 rdmsrl(MSR_FAM10H_NODE_ID, value); in amd_get_topology() 474 rdmsrl(MSR_K7_HWCR, val); in bsp_init_amd() 626 rdmsrl(0xc0011005, value); in init_amd_bd() 865 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); in cpu_has_amd_erratum() 869 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), in cpu_has_amd_erratum()
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D | perf_event_amd_ibs.c | 332 rdmsrl(event->hw.config_base, *config); in perf_ibs_event_update() 398 rdmsrl(hwc->config_base, config); in perf_ibs_stop() 541 rdmsrl(msr, *buf); in perf_ibs_handle_irq() 562 rdmsrl(msr + offset, *buf++); in perf_ibs_handle_irq() 720 rdmsrl(MSR_AMD64_IBSCTL, val); in ibs_eilvt_valid() 837 rdmsrl(MSR_AMD64_IBSCTL, val); in get_ibs_lvt_offset()
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D | perf_event.c | 502 rdmsrl(x86_pmu_config_addr(idx), val); in x86_pmu_disable_all() 1118 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); in perf_event_print_debug() 1119 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); in perf_event_print_debug() 1120 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); in perf_event_print_debug() 1121 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); in perf_event_print_debug() 1122 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); in perf_event_print_debug() 1134 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); in perf_event_print_debug() 1135 rdmsrl(x86_pmu_event_addr(idx), pmc_count); in perf_event_print_debug() 1147 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); in perf_event_print_debug()
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D | intel.c | 140 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); in early_init_intel() 488 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); in init_intel()
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D | perf_event_intel_rapl.c | 126 rdmsrl(event->hw.event_base, raw); in rapl_read_counter() 150 rdmsrl(event->hw.event_base, new_raw_count); in rapl_event_update()
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/arch/x86/kernel/ |
D | mmconf-fam10h_64.c | 98 rdmsrl(address, val); in get_fam10h_pci_mmconf_base() 106 rdmsrl(address, val); in get_fam10h_pci_mmconf_base() 178 rdmsrl(address, val); in fam10h_check_enable_mmcfg()
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D | process_64.c | 87 rdmsrl(MSR_FS_BASE, fs); in __show_regs() 88 rdmsrl(MSR_GS_BASE, gs); in __show_regs() 89 rdmsrl(MSR_KERNEL_GS_BASE, shadowgs); in __show_regs() 611 rdmsrl(MSR_FS_BASE, base); in do_arch_prctl() 625 rdmsrl(MSR_KERNEL_GS_BASE, base); in do_arch_prctl()
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D | amd_nb.c | 152 rdmsrl(address, msr); in amd_get_mmconfig_range()
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/arch/x86/pci/ |
D | amd_bus.c | 195 rdmsrl(address, val); in early_root_info_init() 286 rdmsrl(address, val); in early_root_info_init() 291 rdmsrl(address, val); in early_root_info_init() 333 rdmsrl(MSR_AMD64_NB_CFG, reg); in enable_pci_io_ecs()
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/arch/x86/include/asm/ |
D | virtext.h | 120 rdmsrl(MSR_EFER, efer); in cpu_svm_disable()
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D | apic.h | 143 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); in native_apic_msr_read() 168 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); in native_x2apic_icr_read() 183 rdmsrl(MSR_IA32_APICBASE, msr); in x2apic_enabled()
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D | msr.h | 152 #define rdmsrl(msr, val) \ macro 246 rdmsrl(msr_no, *q); in rdmsrl_on_cpu()
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/arch/x86/realmode/ |
D | init.c | 79 rdmsrl(MSR_EFER, efer); in setup_real_mode()
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/arch/x86/kernel/apic/ |
D | apic_numachip.c | 42 rdmsrl(MSR_FAM10H_NODE_ID, value); in get_apic_id()
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