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Searched refs:writel (Results 1 – 25 of 220) sorted by relevance

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/arch/arm/mach-pxa/
Dcm-x2xx-pci.c136 writel(0x848, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit()
137 writel(0, IT8152_PCI_CFG_DATA); in cmx2xx_pci_preinit()
140 writel(0x840, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit()
141 writel(0, IT8152_PCI_CFG_DATA); in cmx2xx_pci_preinit()
143 writel(0x20, IT8152_GPIO_GPDR); in cmx2xx_pci_preinit()
146 writel(0x4000, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit()
151 writel(0x408C, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit()
152 writel(0x1022, IT8152_PCI_CFG_DATA); in cmx2xx_pci_preinit()
154 writel(0x4080, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit()
155 writel(0x3844d060, IT8152_PCI_CFG_DATA); in cmx2xx_pci_preinit()
[all …]
/arch/arm/mach-netx/
Dtime.c43 writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); in netx_set_mode()
47 writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); in netx_set_mode()
54 writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); in netx_set_mode()
70 writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); in netx_set_mode()
76 writel(0 - evt, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKEVENT)); in netx_set_next_event()
96 writel(COUNTER_BIT(0), NETX_GPIO_IRQ); in netx_timer_interrupt()
115 writel(0, NETX_GPIO_COUNTER_CTRL(0)); in netx_timer_init()
118 writel(0, NETX_GPIO_COUNTER_CURRENT(0)); in netx_timer_init()
120 writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(0)); in netx_timer_init()
123 writel(COUNTER_BIT(0), NETX_GPIO_IRQ); in netx_timer_init()
[all …]
/arch/unicore32/kernel/
Dirq.c68 writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER); in puv3_gpio_type()
69 writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER); in puv3_gpio_type()
79 writel((1 << d->irq), GPIO_GEDR); in puv3_low_gpio_ack()
84 writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR); in puv3_low_gpio_mask()
89 writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR); in puv3_low_gpio_unmask()
95 writel(readl(PM_PWER) | (1 << d->irq), PM_PWER); in puv3_low_gpio_wake()
97 writel(readl(PM_PWER) & ~(1 << d->irq), PM_PWER); in puv3_low_gpio_wake()
126 writel(mask, GPIO_GEDR); in puv3_gpio_handler()
148 writel(mask, GPIO_GEDR); in puv3_high_gpio_ack()
157 writel(readl(GPIO_GRER) & ~mask, GPIO_GRER); in puv3_high_gpio_mask()
[all …]
Dtime.c29 writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER); in puv3_ost0_interrupt()
30 writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR); in puv3_ost0_interrupt()
41 writel(readl(OST_OIER) | OST_OIER_E0, OST_OIER); in puv3_osmr0_set_next_event()
43 writel(next, OST_OSMR0); in puv3_osmr0_set_next_event()
56 writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER); in puv3_osmr0_set_mode()
57 writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR); in puv3_osmr0_set_mode()
96 writel(0, OST_OIER); /* disable any timer interrupts */ in time_init()
97 writel(0, OST_OSSR); /* clear status on all timers */ in time_init()
127 writel(0, OST_OSSR); in puv3_timer_resume()
128 writel(osmr[0], OST_OSMR0); in puv3_timer_resume()
[all …]
Dpci.c32 writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR); in puv3_read_config()
51 writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR); in puv3_write_config()
54 writel((readl(PCICFG_DATA) & ~FMASK(8, (where&3)*8)) in puv3_write_config()
58 writel((readl(PCICFG_DATA) & ~FMASK(16, (where&2)*8)) in puv3_write_config()
62 writel(value, PCICFG_DATA); in puv3_write_config()
77 writel(io_v2p(PKUNITY_PCIBRI_BASE), PCICFG_BRIBASE); in pci_puv3_preinit()
79 writel(0, PCIBRI_AHBCTL0); in pci_puv3_preinit()
80 writel(io_v2p(PKUNITY_PCIBRI_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR0); in pci_puv3_preinit()
81 writel(0xFFFF0000, PCIBRI_AHBAMR0); in pci_puv3_preinit()
82 writel(0, PCIBRI_AHBTAR0); in pci_puv3_preinit()
[all …]
/arch/arm/mach-msm/
Dirq.c70 writel(1 << (d->irq & 31), reg); in msm_irq_ack()
76 writel(1 << (d->irq & 31), reg); in msm_irq_mask()
82 writel(1 << (d->irq & 31), reg); in msm_irq_unmask()
97 writel(readl(preg) | b, preg); in msm_irq_set_type()
99 writel(readl(preg) & (~b), preg); in msm_irq_set_type()
102 writel(readl(treg) | b, treg); in msm_irq_set_type()
106 writel(readl(treg) & (~b), treg); in msm_irq_set_type()
126 writel(0, VIC_INT_TYPE0); in msm_init_irq()
127 writel(0, VIC_INT_TYPE1); in msm_init_irq()
130 writel(0, VIC_INT_POLARITY0); in msm_init_irq()
[all …]
Dproc_comm.c28 writel(1 << irq, MSM_GCC_BASE + 0x8); in msm_a2m_int()
30 writel(1, MSM_CSR_BASE + 0x400 + (irq * 4)); in msm_a2m_int()
88 writel(cmd, base + APP_COMMAND); in msm_proc_comm()
89 writel(data1 ? *data1 : 0, base + APP_DATA1); in msm_proc_comm()
90 writel(data2 ? *data2 : 0, base + APP_DATA2); in msm_proc_comm()
109 writel(PCOM_CMD_IDLE, base + APP_COMMAND); in msm_proc_comm()
/arch/m68k/coldfire/
Dm53xx.c311 writel(0x77777777, MCF_SCM_MPR); in scm_init()
315 writel(0, MCF_SCM_PACRA); in scm_init()
316 writel(0, MCF_SCM_PACRB); in scm_init()
317 writel(0, MCF_SCM_PACRC); in scm_init()
318 writel(0, MCF_SCM_PACRD); in scm_init()
319 writel(0, MCF_SCM_PACRE); in scm_init()
320 writel(0, MCF_SCM_PACRF); in scm_init()
323 writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR); in scm_init()
332 writel(0x10080000, MCF_FBCS1_CSAR); in fbcs_init()
334 writel(0x002A3780, MCF_FBCS1_CSCR); in fbcs_init()
[all …]
/arch/arm/plat-orion/
Dtime.c86 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); in orion_clkevt_next_event()
90 writel(u, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_next_event()
95 writel(delta, timer_base + TIMER1_VAL_OFF); in orion_clkevt_next_event()
102 writel(u, timer_base + TIMER_CTRL_OFF); in orion_clkevt_next_event()
120 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF); in orion_clkevt_mode()
121 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF); in orion_clkevt_mode()
127 writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_mode()
133 writel(u | TIMER1_EN | TIMER1_RELOAD_EN, in orion_clkevt_mode()
140 writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF); in orion_clkevt_mode()
146 writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_mode()
[all …]
Dpcie.c89 writel(stat, base + PCIE_STAT_OFF); in orion_pcie_set_local_bus_nr()
105 writel(reg, base + PCIE_DEBUG_CTRL); in orion_pcie_reset()
115 writel(reg, base + PCIE_DEBUG_CTRL); in orion_pcie_reset()
135 writel(0, base + PCIE_BAR_CTRL_OFF(i)); in orion_pcie_setup_wins()
136 writel(0, base + PCIE_BAR_LO_OFF(i)); in orion_pcie_setup_wins()
137 writel(0, base + PCIE_BAR_HI_OFF(i)); in orion_pcie_setup_wins()
141 writel(0, base + PCIE_WIN04_CTRL_OFF(i)); in orion_pcie_setup_wins()
142 writel(0, base + PCIE_WIN04_BASE_OFF(i)); in orion_pcie_setup_wins()
143 writel(0, base + PCIE_WIN04_REMAP_OFF(i)); in orion_pcie_setup_wins()
146 writel(0, base + PCIE_WIN5_CTRL_OFF); in orion_pcie_setup_wins()
[all …]
/arch/mips/ar7/
Dirq.c54 writel(1 << ((d->irq - ar7_irq_base) % 32), in ar7_unmask_irq()
60 writel(1 << ((d->irq - ar7_irq_base) % 32), in ar7_mask_irq()
66 writel(1 << ((d->irq - ar7_irq_base) % 32), in ar7_ack_irq()
72 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); in ar7_unmask_sec_irq()
77 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); in ar7_mask_sec_irq()
82 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); in ar7_ack_sec_irq()
111 writel(0xffffffff, REG(ECR_OFFSET(0))); in ar7_irq_init()
112 writel(0xff, REG(ECR_OFFSET(32))); in ar7_irq_init()
113 writel(0xffffffff, REG(SEC_ECR_OFFSET)); in ar7_irq_init()
114 writel(0xffffffff, REG(CR_OFFSET(0))); in ar7_irq_init()
[all …]
/arch/arm/mach-integrator/
Dintegrator_ap.c138 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); in irq_resume()
139 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); in irq_resume()
141 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET); in irq_resume()
169 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, in ap_flash_init()
174 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); in ap_flash_init()
178 writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); in ap_flash_init()
179 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); in ap_flash_init()
180 writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); in ap_flash_init()
189 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, in ap_flash_exit()
194 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); in ap_flash_exit()
[all …]
/arch/arm/mach-s3c64xx/
Dsetup-usb-phy.c29 writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); in s3c_usb_otgphy_init()
52 writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK); in s3c_usb_otgphy_init()
55 writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR); in s3c_usb_otgphy_init()
59 writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK, in s3c_usb_otgphy_init()
62 writel(0, S3C_RSTCON); in s3c_usb_otgphy_init()
69 writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN | in s3c_usb_otgphy_exit()
72 writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); in s3c_usb_otgphy_exit()
/arch/arm/mach-cns3xxx/
Dcore.c107 writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET); in cns3xxx_power_off()
126 writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); in cns3xxx_timer_set_mode()
139 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_timer_set_mode()
147 writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); in cns3xxx_timer_set_next_event()
148 writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_timer_set_next_event()
181 writel(val & ~(1 << 2), stat); in cns3xxx_timer_interrupt()
207 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in __cns3xxx_timer_init()
209 writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); in __cns3xxx_timer_init()
212 writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); in __cns3xxx_timer_init()
213 writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); in __cns3xxx_timer_init()
[all …]
/arch/arm/mach-gemini/
Dtime.c50 writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_next_event()
53 writel(cycles, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); in gemini_timer_set_next_event()
54 writel(cycles, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); in gemini_timer_set_next_event()
57 writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_next_event()
71 writel(period, in gemini_timer_set_mode()
73 writel(period, in gemini_timer_set_mode()
78 writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_mode()
91 writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_mode()
159 writel(0xffffffff, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE))); in gemini_timer_init()
160 writel(0xffffffff, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER1_BASE))); in gemini_timer_init()
[all …]
/arch/arm/mach-orion5x/
Dtsx09-common.c36 writel(0x83, UART1_REG(LCR)); in qnap_tsx09_power_off()
37 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_tsx09_power_off()
38 writel((divisor >> 8) & 0xff, UART1_REG(DLM)); in qnap_tsx09_power_off()
39 writel(0x03, UART1_REG(LCR)); in qnap_tsx09_power_off()
40 writel(0x00, UART1_REG(IER)); in qnap_tsx09_power_off()
41 writel(0x00, UART1_REG(FCR)); in qnap_tsx09_power_off()
42 writel(0x00, UART1_REG(MCR)); in qnap_tsx09_power_off()
45 writel('A', UART1_REG(TX)); in qnap_tsx09_power_off()
/arch/xtensa/variants/s6000/include/variant/
Ddmac.h156 writel(m, dmac + S6_DMA_TERMCNTIRQCLR); in s6dmac_termcnt_irq()
165 writel(m, dmac + S6_DMA_PENDCNTIRQCLR); in s6dmac_pendcnt_irq()
173 writel(1 << chan, dmac + S6_DMA_LOWWMRKIRQCLR); in s6dmac_lowwmark_irq()
189 writel(n, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB); in s6dmac_set_terminal_count()
216 writel(readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL) in s6dmac_disable_chan()
228 writel(comchunk, DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK); in s6dmac_set_stride_skip()
229 writel(srcskip, DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP); in s6dmac_set_stride_skip()
230 writel(dstskip, DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP); in s6dmac_set_stride_skip()
245 writel(1, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB); in s6dmac_enable_chan()
246 writel(0, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTTMO); in s6dmac_enable_chan()
[all …]
/arch/arm/mach-sunxi/
Dplatsmp.c83 writel(virt_to_phys(secondary_startup), in sun6i_smp_boot_secondary()
87 writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); in sun6i_smp_boot_secondary()
91 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG); in sun6i_smp_boot_secondary()
95 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); in sun6i_smp_boot_secondary()
99 writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu)); in sun6i_smp_boot_secondary()
104 writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG); in sun6i_smp_boot_secondary()
108 writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); in sun6i_smp_boot_secondary()
112 writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); in sun6i_smp_boot_secondary()
/arch/arm/mach-mvebu/
Dcoherency.c111 writel(0x1, coherency_wa_buf[idx]); in mvebu_hwcc_armada375_sync_io_barrier_wa()
120 writel(0x1, xor_base + XOR_ACTIVATION(idx)); in mvebu_hwcc_armada375_sync_io_barrier_wa()
176 writel(0, xor_base + WINDOW_BASE(i)); in armada_375_coherency_init_wa()
177 writel(0, xor_base + WINDOW_SIZE(i)); in armada_375_coherency_init_wa()
179 writel(0, xor_base + WINDOW_REMAP_HIGH(i)); in armada_375_coherency_init_wa()
184 writel((cs->base & 0xffff0000) | in armada_375_coherency_init_wa()
187 writel((cs->size - 1) & 0xffff0000, xor_base + WINDOW_SIZE(i)); in armada_375_coherency_init_wa()
193 writel(win_enable, xor_base + WINDOW_BAR_ENABLE(0)); in armada_375_coherency_init_wa()
194 writel(win_enable, xor_base + WINDOW_BAR_ENABLE(1)); in armada_375_coherency_init_wa()
195 writel(0, xor_base + WINDOW_OVERRIDE_CTRL(0)); in armada_375_coherency_init_wa()
[all …]
/arch/mips/jz4740/
Dtimer.c28 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); in jz4740_timer_enable_watchdog()
34 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); in jz4740_timer_disable_watchdog()
46 writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET); in jz4740_timer_init()
49 writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET); in jz4740_timer_init()
/arch/arm/common/
Dtimer-sp.c96 writel(0, base + TIMER_CTRL); in __sp804_clocksource_and_sched_clock_init()
97 writel(0xffffffff, base + TIMER_LOAD); in __sp804_clocksource_and_sched_clock_init()
98 writel(0xffffffff, base + TIMER_VALUE); in __sp804_clocksource_and_sched_clock_init()
99 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, in __sp804_clocksource_and_sched_clock_init()
123 writel(1, clkevt_base + TIMER_INTCLR); in sp804_timer_interrupt()
135 writel(ctrl, clkevt_base + TIMER_CTRL); in sp804_set_mode()
139 writel(clkevt_reload, clkevt_base + TIMER_LOAD); in sp804_set_mode()
154 writel(ctrl, clkevt_base + TIMER_CTRL); in sp804_set_mode()
162 writel(next, clkevt_base + TIMER_LOAD); in sp804_set_next_event()
163 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); in sp804_set_next_event()
[all …]
/arch/arm/mach-highbank/
Dsysregs.h58 writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_set_pwr_suspend()
64 writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_set_pwr_shutdown()
70 writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_set_pwr_soft_reset()
76 writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_set_pwr_hard_reset()
82 writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_clear_pwr_request()
/arch/arm/mach-prima2/
Drstc.c45 writel(readl(sirfsoc_rstc_base + in sirfsoc_reset_module()
49 writel(readl(sirfsoc_rstc_base + in sirfsoc_reset_module()
61 writel(1 << reset_bit, in sirfsoc_reset_module()
64 writel(1 << reset_bit, in sirfsoc_reset_module()
86 writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base); in sirfsoc_restart()
/arch/xtensa/variants/s6000/
Ddmac.c90 writel(tmp, dmac + S6_DMA_TERMCNTIRQCLR); in s6dmac_int_sources()
95 writel(tmp, dmac + S6_DMA_PENDCNTIRQCLR); in s6dmac_int_sources()
100 writel(tmp, dmac + S6_DMA_LOWWMRKIRQCLR); in s6dmac_int_sources()
105 writel(tmp, dmac + S6_DMA_INTCLEAR0); in s6dmac_int_sources()
125 writel(tmp, dmac + S6_DMA_INTCLEAR1); in s6dmac_int_sources()
146 writel(S6_DMA_INT1_MASTER_MASK << S6_DMA_INT1_MASTER, in dmac_init()
153 writel(m0start, dmac + S6_DMA_MASTER0START); in dmac_master()
154 writel(m0end - 1, dmac + S6_DMA_MASTER0END); in dmac_master()
155 writel(m1start, dmac + S6_DMA_MASTER1START); in dmac_master()
156 writel(m1end - 1, dmac + S6_DMA_MASTER1END); in dmac_master()
/arch/arm/mach-dove/
Dmpp.c77 writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE); in dove_mpp_cfg_nfc()
114 writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); in dove_mpp_cfg_au1()
115 writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1); in dove_mpp_cfg_au1()
116 writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE); in dove_mpp_cfg_au1()
117 writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2); in dove_mpp_cfg_au1()
143 writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); in dove_mpp_conf_grp()

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