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Searched refs:BIT0 (Results 1 – 25 of 56) sorted by relevance

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/drivers/net/wireless/rtlwifi/rtl8821ae/
Dpwrseq.h60 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
63 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
118 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
177 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
203 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
269 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
316 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
393 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
411 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \
[all …]
/drivers/scsi/
Dtmscsim.h192 #define BIT0 0x00000001 macro
195 #define UNIT_ALLOCATED BIT0
201 #define DASD_SUPPORT BIT0
207 #define SRB_WAIT BIT0
224 #define SRB_OK BIT0
232 #define RESET_DEV BIT0
237 #define ABORT_DEV_ BIT0
246 #define AUTO_REQSENSE BIT0
279 #define SYNC_ENABLE BIT0
334 #define PARITY_CHK_ BIT0
[all …]
Ddc395x.h75 #define BIT0 0x00000001 macro
78 #define UNIT_ALLOCATED BIT0
84 #define DASD_SUPPORT BIT0
120 #define RESET_DEV BIT0
125 #define ABORT_DEV_ BIT0
128 #define SRB_OK BIT0
142 #define AUTO_REQSENSE BIT0
173 #define SYNC_NEGO_ENABLE BIT0
629 #define MORE2_DRV BIT0
/drivers/staging/rtl8188eu/include/
Dpwrseq.h71 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0|BIT1, 0}, \
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, \
86 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, \
140 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, \
153 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, \
187 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, \
200 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, \
216 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, \
254 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, \
298 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, \
Drtl8188e_spec.h26 #define BIT0 0x00000001 macro
504 #define HSIMR_GPIO12_0_INT_EN BIT0
511 #define HSISR_GPIO12_0_INT BIT0
540 #define CMD_INIT_LLT BIT0
551 #define RRSR_1M BIT0
574 #define HAL92C_WOL_PTK_UPDATE_EVENT BIT0
610 #define WOW_PMEN BIT0 /* Power management Enable. */
642 #define IMR_ROK_88E BIT0 /* Receive DMA OK */
705 #define StopVO BIT0
732 #define RCR_AAP BIT0 /* Accept all unicast packet */
[all …]
Dodm.h417 ODM_BB_DIG = BIT0,
463 ODM_RF_TX_A = BIT0,
501 ODM_NO_LINK = BIT0,
515 ODM_WM_B = BIT0,
526 ODM_BAND_2_4G = BIT0,
Drtw_sreset.h33 #define USB_VEN_REQ_CMD_FAIL BIT0
Dodm_reg.h115 #define BIT_FA_RESET BIT0
/drivers/staging/vt6655/
D80211hdr.h37 #define BIT0 0x00000001 macro
158 #define WLAN_GET_FC_PRVER(n) (((unsigned short)(n) >> 8) & (BIT0 | BIT1))
171 #define WLAN_GET_SEQ_FRGNUM(n) (((unsigned short)(n) >> 8) & (BIT0|BIT1|BIT2|BIT3))
172 #define WLAN_GET_SEQ_SEQNUM(n) ((((unsigned short)(n) >> 8) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
175 #define WLAN_GET_CAP_INFO_ESS(n) (((n) >> 8) & BIT0)
191 #define WLAN_GET_FC_PRVER(n) (((unsigned short)(n)) & (BIT0 | BIT1))
204 #define WLAN_GET_SEQ_FRGNUM(n) (((unsigned short)(n)) & (BIT0|BIT1|BIT2|BIT3))
205 #define WLAN_GET_SEQ_SEQNUM(n) ((((unsigned short)(n)) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
208 #define WLAN_GET_CAP_INFO_ESS(n) ((n) & BIT0)
253 #define WLAN_GET_ERP_NONERP_PRESENT(n) ((n) & BIT0)
[all …]
Dhostap.h34 #define WLAN_RATE_1M BIT0
/drivers/video/fbdev/via/
Ddvi.c59 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
66 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
349 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
352 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
359 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
377 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
384 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
391 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
409 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); in viafb_dvi_enable()
410 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
[all …]
Dlcd.c359 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
534 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
577 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
599 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0); in viafb_lcd_set_mode()
666 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
668 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
675 viafb_write_reg_mask(CR91, VIACR, 0, BIT0); in integrated_lvds_enable()
684 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0); in integrated_lvds_enable()
760 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
859 bdithering = BIT0; in fill_lcd_format()
[all …]
Dvia_utility.c166 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_set_gamma_table()
183 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_set_gamma_table()
221 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_get_gamma_table()
Dhw.c487 viafb_write_reg_mask(CR47, VIACR, 0, BIT0); in viafb_unlock_crt()
964 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); in load_fix_bit_crtc_reg()
1001 reg_mask = reg_mask | (BIT0 << j); in viafb_load_reg()
1002 get_bit = (timing_value & (BIT0 << bit_num)); in viafb_load_reg()
1682 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); in viafb_init_dac()
1696 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_init_dac()
1703 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); in viafb_init_dac()
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h144 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
163 #define RCR_AAP BIT0
215 #define SCR_TxUseDK BIT0
242 #define IMR_ROK BIT0
245 #define TPPoll_BKQ BIT0
285 #define AcmHw_HwEn BIT0
293 #define AcmFw_BeqStatus BIT0
346 #define BW_OPMODE_11J BIT0
375 #define RRSR_1M BIT0
/drivers/staging/rtl8192u/
Dr8192U_hw.h160 #define RCR_AAP BIT0 // Accept all unicast packet
183 #define SCR_TxUseDK BIT0 //Force Tx Use Default Key
229 #define AcmHw_HwEn BIT0
284 #define BW_OPMODE_11J BIT0
307 #define RRSR_1M BIT0
/drivers/net/wireless/rtlwifi/btcoexist/
Dhalbtc8821a2ant.c344 h2c_parameter[0] |= BIT0; /* trigger */ in halbtc8821a2ant_query_bt_info()
628 h2c_parameter[1] |= BIT0; in btc8821a2ant_set_fw_bt_lna_constr()
710 h2c_parameter[0] |= BIT0; in halbtc8821a2ant_set_bt_auto_report()
827 h2c_parameter[1] |= BIT0; in btc8821a2ant_SetSwPenTxRateAdapt()
1028 h2c_parameter[0] |= BIT0;/* function enable */ in halbtc8821a2ant_set_fw_ignore_wlan_act()
2573 if (bt_info_ext&BIT0) { in halbtc8821a2ant_action_a2dp_pan_hs()
2596 if (bt_info_ext&BIT0) { in halbtc8821a2ant_action_a2dp_pan_hs()
2808 if (bt_info_ext&BIT0) { in halbtc8821a2ant_action_pan_edr_a2dp()
2818 if (bt_info_ext&BIT0) { in halbtc8821a2ant_action_pan_edr_a2dp()
2846 if (bt_info_ext&BIT0) { in halbtc8821a2ant_action_pan_edr_a2dp()
[all …]
Dhalbtc8723b1ant.h37 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
40 (((_BT_INFO_EXT_&BIT0)) ? true : false)
Dhalbtc8821a1ant.h39 #define BT_INFO_8821A_1ANT_B_CONNECTION BIT0
42 (((_BT_INFO_EXT_&BIT0)) ? true : false)
Dhalbtcoutsrc.h97 #define INTF_INIT BIT0
101 #define ALGO_BT_RSSI_STATE BIT0
113 #define WIFI_STA_CONNECTED BIT0
Dhalbt_precomp.h48 #define BIT0 0x00000001 macro
/drivers/staging/rtl8192e/
Drtl819x_Qos.h24 #define BIT0 0x00000001 macro
236 #define GET_VO_UAPSD(_apsd) ((_apsd) & BIT0)
237 #define SET_VO_UAPSD(_apsd) ((_apsd) |= BIT0)
/drivers/staging/rtl8192u/ieee80211/
Drtl819x_Qos.h4 #define BIT0 0x00000001 macro
378 #define GET_VO_UAPSD(_apsd) ((_apsd) & BIT0)
379 #define SET_VO_UAPSD(_apsd) ((_apsd) |= BIT0)
/drivers/tty/
Dsynclink_gt.c215 …a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
222 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
383 #define MASK_FRAMING BIT0
425 #define IRQ_MASTER BIT0
1882 if ((status = *(p+1) & (BIT1 + BIT0))) { in rx_async()
1885 else if (status & BIT0) in rx_async()
1892 else if (status & BIT0) in rx_async()
2105 if (status & BIT0) { in ri_change()
3911 if (!(rd_reg32(info, RDCSR) & BIT0)) in rdma_reset()
3924 if (!(rd_reg32(info, TDCSR) & BIT0)) in tdma_reset()
[all …]
/drivers/staging/rtl8188eu/core/
Drtw_efuse.c400 if (!(word_en&BIT0)) { in Efuse_WordEnableDataWrite()
408 badworden &= (~BIT0); in Efuse_WordEnableDataWrite()
744 if (((pTargetPkt->word_en & BIT0) == 0) && in wordEnMatched()
745 ((pCurPkt->word_en & BIT0) == 0)) in wordEnMatched()
746 match_word_en &= ~BIT0; /* enable word 0 */ in wordEnMatched()

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