| /drivers/gpu/drm/nouveau/core/subdev/clock/ |
| D | pllnv04.c | 152 int M1, N1, M2, N2, log2P; in getMNP_double() local
178 for (M2 = minM2; M2 <= maxM2; M2++) { in getMNP_double()
179 if (calcclk1/M2 < minU2) in getMNP_double()
181 if (calcclk1/M2 > maxU2) in getMNP_double()
185 N2 = (clkP * M2 + calcclk1/2) / calcclk1; in getMNP_double()
193 if (N2/M2 < 4 || N2/M2 > 10) in getMNP_double()
196 calcclk2 = calcclk1 * N2 / M2; in getMNP_double()
215 *pM2 = M2; in getMNP_double()
229 int *N1, int *M1, int *N2, int *M2, int *P) in nv04_pll_calc() argument
237 *M2 = 1; in nv04_pll_calc()
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| D | nv40.c | 70 int M2 = (coef & 0x00ff0000) >> 16; in read_pll_2() local
79 if (M2) in read_pll_2()
80 clk = clk * N2 / M2; in read_pll_2()
131 int *N1, int *M1, int *N2, int *M2, int *log2P) in nv40_clock_calc_pll() argument
144 ret = nv04_pll_calc(nv_subdev(priv), &pll, clk, N1, M1, N2, M2, log2P); in nv40_clock_calc_pll()
156 int N1, M1, N2, M2, log2P; in nv40_clock_calc() local
161 &N1, &M1, &N2, &M2, &log2P); in nv40_clock_calc()
165 if (N2 == M2) { in nv40_clock_calc()
170 priv->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; in nv40_clock_calc()
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| D | nv04.c | 40 int N1, M1, N2, M2, P; in nv04_clock_pll_calc() local
41 int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P); in nv04_clock_pll_calc()
47 pv->M2 = M2; in nv04_clock_pll_calc()
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| D | nv50.c | 162 int N1, N2, M1, M2; in read_pll() local
171 M2 = (coef & 0x00ff0000) >> 16; in read_pll()
177 if (M2) in read_pll()
178 freq = freq * N2 / M2; in read_pll()
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| D | pll.h | 5 int *N1, int *M1, int *N2, int *M2, int *P);
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| /drivers/gpu/drm/nouveau/core/subdev/devinit/ |
| D | nv04.c | 204 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */ in setPLL_double_highregs()
211 (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4; in setPLL_double_highregs()
290 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; in setPLL_double_lowregs()
356 int N1, M1, N2, M2, P; in nv04_devinit_pll_set() local
364 &N1, &M1, &N2, &M2, &P); in nv04_devinit_pll_set()
372 pv.M2 = M2; in nv04_devinit_pll_set()
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| D | nv50.c | 39 int N1, M1, N2, M2, P; in nv50_devinit_pll_set() local
48 ret = nv04_pll_calc(nv_subdev(devinit), &info, freq, &N1, &M1, &N2, &M2, &P); in nv50_devinit_pll_set()
60 (M2 << 16) | N2); in nv50_devinit_pll_set()
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| /drivers/gpu/drm/nouveau/core/subdev/fb/ |
| D | ramnv40.c | 43 int N1, M1, N2, M2; in nv40_ram_calc() local
53 &N1, &M1, &N2, &M2, &log2P); in nv40_ram_calc()
59 if (N2 == M2) { in nv40_ram_calc()
64 ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; in nv40_ram_calc()
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| D | ramnv50.c | 78 int N1, M1, N2, M2, P; in nv50_ram_calc() local
139 &N1, &M1, &N2, &M2, &P); in nv50_ram_calc()
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| D | ramnve0.c | 140 int N2, M2, P2; member
166 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2); in r1373f4_init()
1001 &ram->N2, NULL, &ram->M2, &ram->P2); in nve0_ram_calc_xits()
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| /drivers/isdn/hardware/avm/ |
| D | Kconfig | 38 tristate "AVM B1/M1/M2 PCMCIA support"
44 tristate "AVM B1/M1/M2 PCMCIA cs module"
47 Enable the PCMCIA client driver for the AVM B1/M1/M2
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| /drivers/gpu/drm/nouveau/core/include/subdev/bios/ |
| D | pll.h | 9 uint8_t N1, M1, N2, M2; member
11 uint8_t M1, N1, M2, N2;
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | hw.c | 141 pllvals->N2 = pllvals->M2 = 1; in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
208 if (!pv->M1 || !pv->M2) in nouveau_hw_pllvals_to_clk()
211 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; in nouveau_hw_pllvals_to_clk()
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| D | crtc.c | 159 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); in nv_crtc_calc_state_ext()
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| /drivers/iommu/ |
| D | Kconfig | 280 R-Mobile APE6 and R-Car H2/M2 SoCs.
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| /drivers/hwmon/ |
| D | Kconfig | 537 the x3350, x3550, x3650, x3655, x3755, x3850 M2, x3950 M2,
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