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Searched refs:clkrate (Results 1 – 10 of 10) sorted by relevance

/drivers/w1/masters/
Dmxc_w1.c102 unsigned long clkrate; in mxc_w1_probe() local
116 clkrate = clk_get_rate(mdev->clk); in mxc_w1_probe()
117 if (clkrate < 10000000) in mxc_w1_probe()
121 clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000); in mxc_w1_probe()
122 clkrate /= clkdiv; in mxc_w1_probe()
123 if ((clkrate < 980000) || (clkrate > 1020000)) in mxc_w1_probe()
125 "Incorrect time base frequency %lu Hz\n", clkrate); in mxc_w1_probe()
/drivers/i2c/busses/
Di2c-stu300.c490 static int stu300_set_clk(struct stu300_dev *dev, unsigned long clkrate) in stu300_set_clk() argument
498 stu300_clktable[i].rate < clkrate) in stu300_set_clk()
503 "(%lu Hz).\n", i ? "high" : "low", clkrate); in stu300_set_clk()
511 "virtbase %p\n", clkrate, dev->speed, dev->virtbase); in stu300_set_clk()
515 val = ((clkrate/dev->speed) - 9)/3 + 1; in stu300_set_clk()
518 val = ((clkrate/dev->speed) - 7)/2 + 1; in stu300_set_clk()
523 clkrate); in stu300_set_clk()
530 clkrate); in stu300_set_clk()
559 unsigned long clkrate; in stu300_init_hw() local
576 clkrate = clk_get_rate(dev->clk); in stu300_init_hw()
[all …]
Di2c-s3c2410.c113 unsigned long clkrate; member
865 i2c->clkrate = clkin; in s3c24xx_i2c_clockrate()
929 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; in s3c24xx_i2c_cpufreq_transition()
Di2c-omap.c1132 dev->speed = pdata->clkrate; in omap_i2c_probe()
/drivers/mtd/nand/
Dlpc32xx_mlc.c230 uint32_t clkrate, tmp; in lpc32xx_nand_setup() local
237 clkrate = clk_get_rate(host->clk); in lpc32xx_nand_setup()
238 if (clkrate == 0) in lpc32xx_nand_setup()
239 clkrate = 104000000; in lpc32xx_nand_setup()
255 tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1); in lpc32xx_nand_setup()
256 tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1); in lpc32xx_nand_setup()
257 tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1); in lpc32xx_nand_setup()
258 tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1); in lpc32xx_nand_setup()
259 tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low); in lpc32xx_nand_setup()
260 tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1); in lpc32xx_nand_setup()
[all …]
Dlpc32xx_slc.c224 uint32_t clkrate, tmp; in lpc32xx_nand_setup() local
237 clkrate = clk_get_rate(host->clk); in lpc32xx_nand_setup()
238 if (clkrate == 0) in lpc32xx_nand_setup()
239 clkrate = LPC32XX_DEF_BUS_RATE; in lpc32xx_nand_setup()
243 SLCTAC_WWIDTH(1 + (clkrate / host->ncfg->wwidth)) | in lpc32xx_nand_setup()
244 SLCTAC_WHOLD(1 + (clkrate / host->ncfg->whold)) | in lpc32xx_nand_setup()
245 SLCTAC_WSETUP(1 + (clkrate / host->ncfg->wsetup)) | in lpc32xx_nand_setup()
247 SLCTAC_RWIDTH(1 + (clkrate / host->ncfg->rwidth)) | in lpc32xx_nand_setup()
248 SLCTAC_RHOLD(1 + (clkrate / host->ncfg->rhold)) | in lpc32xx_nand_setup()
249 SLCTAC_RSETUP(1 + (clkrate / host->ncfg->rsetup)); in lpc32xx_nand_setup()
Ds3c2410.c269 unsigned long clkrate = clk_get_rate(info->clk); in s3c2410_nand_setrate() local
275 info->clk_rate = clkrate; in s3c2410_nand_setrate()
276 clkrate /= 1000; /* turn clock into kHz for ease of use */ in s3c2410_nand_setrate()
279 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max); in s3c2410_nand_setrate()
280 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8); in s3c2410_nand_setrate()
281 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8); in s3c2410_nand_setrate()
295 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), in s3c2410_nand_setrate()
296 twrph1, to_ns(twrph1, clkrate)); in s3c2410_nand_setrate()
/drivers/mmc/host/
Dpxamci.c59 unsigned long clkrate; member
193 clks = (unsigned long long)data->timeout_ns * host->clkrate; in pxamci_setup_data()
473 unsigned long rate = host->clkrate; in pxamci_set_ios()
685 host->clkrate = clk_get_rate(host->clk); in pxamci_probe()
690 mmc->f_min = (host->clkrate + 63) / 64; in pxamci_probe()
691 mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate; in pxamci_probe()
/drivers/gpu/ipu-v3/
Dipu-di.c453 unsigned long rate, clkrate; in ipu_di_config_clock() local
456 clkrate = clk_get_rate(di->clk_ipu); in ipu_di_config_clock()
457 div = (clkrate + sig->pixelclock / 2) / sig->pixelclock; in ipu_di_config_clock()
458 rate = clkrate / div; in ipu_di_config_clock()
/drivers/spi/
Dspi-fsl-dspi.c141 unsigned long clkrate) in hz_to_spi_baud() argument
151 temp = clkrate / 2 / speed_hz; in hz_to_spi_baud()
163 ,we use the max prescaler value.\n", speed_hz, clkrate); in hz_to_spi_baud()