Searched refs:clock_type (Results 1 – 16 of 16) sorted by relevance
129 switch(port->settings.clock_type) { in pci200_set_iface()221 if (new_line.clock_type != CLOCK_EXT && in pci200_ioctl()222 new_line.clock_type != CLOCK_TXFROMRX && in pci200_ioctl()223 new_line.clock_type != CLOCK_INT && in pci200_ioctl()224 new_line.clock_type != CLOCK_TXINT) in pci200_ioctl()398 port->settings.clock_type = CLOCK_EXT; in pci200_pci_init_one()
158 switch(port->settings.clock_type) { in c101_set_iface()265 if (new_line.clock_type != CLOCK_EXT && in c101_ioctl()266 new_line.clock_type != CLOCK_TXFROMRX && in c101_ioctl()267 new_line.clock_type != CLOCK_INT && in c101_ioctl()268 new_line.clock_type != CLOCK_TXINT) in c101_ioctl()380 card->settings.clock_type = CLOCK_EXT; in c101_run()
130 switch(port->settings.clock_type) { in pc300_set_iface()246 if (new_line.clock_type != CLOCK_EXT && in pc300_ioctl()247 new_line.clock_type != CLOCK_TXFROMRX && in pc300_ioctl()248 new_line.clock_type != CLOCK_INT && in pc300_ioctl()249 new_line.clock_type != CLOCK_TXINT) in pc300_ioctl()458 port->settings.clock_type = CLOCK_EXT; in pc300_pci_init_one()
176 switch(port->settings.clock_type) { in n2_set_iface()283 if (new_line.clock_type != CLOCK_EXT && in n2_ioctl()284 new_line.clock_type != CLOCK_TXFROMRX && in n2_ioctl()285 new_line.clock_type != CLOCK_INT && in n2_ioctl()286 new_line.clock_type != CLOCK_TXINT) in n2_ioctl()473 port->settings.clock_type = CLOCK_EXT; in n2_run()
62 unsigned int clock_type; member359 line.clock_type = get_status(port)->clocking; in wanxl_ioctl()377 if (line.clock_type != CLOCK_EXT && in wanxl_ioctl()378 line.clock_type != CLOCK_TXFROMRX) in wanxl_ioctl()384 get_status(port)->clocking = line.clock_type; in wanxl_ioctl()
266 unsigned int clock_type, clock_rate, loopback; member403 if (port->clock_type == CLOCK_INT) in hss_config()1265 new_line.clock_type = port->clock_type; in hss_hdlc_ioctl()1279 clk = new_line.clock_type; in hss_hdlc_ioctl()1289 port->clock_type = clk; /* Update settings */ in hss_hdlc_ioctl()1355 port->clock_type = CLOCK_EXT; in hss_init_one()
1910 switch (sync.clock_type) { in fst_set_iface()1969 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) == in fst_get_iface()
998 if (settings->loopback && (settings->clock_type != CLOCK_INT)) { in dscc4_loopback_check()
437 unsigned int clock_type; in sm501fb_set_par_common() local448 clock_type = SM501_CLOCK_V2XCLK; in sm501fb_set_par_common()454 clock_type = SM501_CLOCK_P2XCLK; in sm501fb_set_par_common()461 clock_type = 0; in sm501fb_set_par_common()507 sm501pixclock = sm501_set_clock(fbi->dev->parent, clock_type, in sm501fb_set_par_common()
4138 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; in hdlcdev_ioctl()4139 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; in hdlcdev_ioctl()4140 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; in hdlcdev_ioctl()4141 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; in hdlcdev_ioctl()4142 default: new_line.clock_type = CLOCK_DEFAULT; in hdlcdev_ioctl()4159 switch (new_line.clock_type) in hdlcdev_ioctl()
2785 u8 clock_type, in radeon_atom_get_clock_dividers() argument2803 args.v1.ucAction = clock_type; in radeon_atom_get_clock_dividers()2817 args.v2.ucAction = clock_type; in radeon_atom_get_clock_dividers()2832 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { in radeon_atom_get_clock_dividers()2833 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); in radeon_atom_get_clock_dividers()2851 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); in radeon_atom_get_clock_dividers()2882 args.v6_in.ulClock.ulComputeClockFlag = clock_type; in radeon_atom_get_clock_dividers()
286 u8 clock_type,
1655 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; in hdlcdev_ioctl()1656 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; in hdlcdev_ioctl()1657 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; in hdlcdev_ioctl()1658 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; in hdlcdev_ioctl()1659 default: new_line.clock_type = CLOCK_DEFAULT; in hdlcdev_ioctl()1676 switch (new_line.clock_type) in hdlcdev_ioctl()
1771 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; in hdlcdev_ioctl()1772 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; in hdlcdev_ioctl()1773 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; in hdlcdev_ioctl()1774 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; in hdlcdev_ioctl()1775 default: new_line.clock_type = CLOCK_DEFAULT; in hdlcdev_ioctl()1792 switch (new_line.clock_type) in hdlcdev_ioctl()
7867 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; in hdlcdev_ioctl()7868 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; in hdlcdev_ioctl()7869 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; in hdlcdev_ioctl()7870 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; in hdlcdev_ioctl()7871 default: new_line.clock_type = CLOCK_DEFAULT; in hdlcdev_ioctl()7888 switch (new_line.clock_type) in hdlcdev_ioctl()
3734 const char *clock_type; in octeon_usb_probe() local3767 "refclk-type", &clock_type); in octeon_usb_probe()3769 if (!i && strcmp("crystal", clock_type) == 0) in octeon_usb_probe()