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Searched refs:clr (Results 1 – 25 of 46) sorted by relevance

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/drivers/net/wireless/ath/ath9k/
Dar9003_wow.c112 u32 set, clr; in ath9k_hw_wow_apply_pattern() local
161 clr = AR_WOW_LENGTH1_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
162 REG_RMW(ah, AR_WOW_LENGTH1, set, clr); in ath9k_hw_wow_apply_pattern()
167 clr = AR_WOW_LENGTH2_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
168 REG_RMW(ah, AR_WOW_LENGTH2, set, clr); in ath9k_hw_wow_apply_pattern()
245 u32 set, clr; in ath9k_hw_wow_enable() local
267 clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE; in ath9k_hw_wow_enable()
268 REG_RMW(ah, AR_WA, set, clr); in ath9k_hw_wow_enable()
282 clr = AR_PMCTRL_WOW_PME_CLR; in ath9k_hw_wow_enable()
283 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr); in ath9k_hw_wow_enable()
[all …]
Deeprom_4k.c1064 u32 pwrctrl, mask, clr; in ath9k_hw_4k_set_board_values() local
1068 clr = mask * 0x1f; in ath9k_hw_4k_set_board_values()
1069 REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
1070 REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
1071 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
1075 clr = mask * 0x1f; in ath9k_hw_4k_set_board_values()
1076 REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
1080 clr = mask * 0x1f; in ath9k_hw_4k_set_board_values()
1081 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
1082 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr); in ath9k_hw_4k_set_board_values()
Dinit.c130 u32 set, u32 clr) in __ath9k_reg_rmw() argument
135 val &= ~clr; in __ath9k_reg_rmw()
142 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) in ath9k_reg_rmw() argument
152 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); in ath9k_reg_rmw()
155 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); in ath9k_reg_rmw()
/drivers/clocksource/
Dtime-armada-370-xp.c88 static void local_timer_ctrl_clrset(u32 clr, u32 set) in local_timer_ctrl_clrset() argument
90 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, in local_timer_ctrl_clrset()
172 u32 clr = 0, set = 0; in armada_370_xp_timer_setup() local
178 clr = TIMER0_25MHZ; in armada_370_xp_timer_setup()
179 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_setup()
228 u32 clr = 0, set = 0; in armada_370_xp_timer_common_init() local
239 clr = TIMER0_25MHZ; in armada_370_xp_timer_common_init()
242 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); in armada_370_xp_timer_common_init()
243 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_common_init()
/drivers/gpu/drm/radeon/
Dradeon_ioc32.c110 drm_radeon_clear_t __user *clr; in compat_radeon_cp_clear() local
115 clr = compat_alloc_user_space(sizeof(*clr)); in compat_radeon_cp_clear()
116 if (!access_ok(VERIFY_WRITE, clr, sizeof(*clr)) in compat_radeon_cp_clear()
117 || __put_user(clr32.flags, &clr->flags) in compat_radeon_cp_clear()
118 || __put_user(clr32.clear_color, &clr->clear_color) in compat_radeon_cp_clear()
119 || __put_user(clr32.clear_depth, &clr->clear_depth) in compat_radeon_cp_clear()
120 || __put_user(clr32.color_mask, &clr->color_mask) in compat_radeon_cp_clear()
121 || __put_user(clr32.depth_mask, &clr->depth_mask) in compat_radeon_cp_clear()
123 &clr->depth_boxes)) in compat_radeon_cp_clear()
126 return drm_ioctl(file, DRM_IOCTL_RADEON_CLEAR, (unsigned long)clr); in compat_radeon_cp_clear()
/drivers/gpio/
Dgpio-generic.c346 void __iomem *clr) in bgpio_setup_io() argument
353 if (set && clr) { in bgpio_setup_io()
355 bgc->reg_clr = clr; in bgpio_setup_io()
357 } else if (set && !clr) { in bgpio_setup_io()
408 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, in bgpio_init() argument
427 ret = bgpio_setup_io(bgc, dat, set, clr); in bgpio_init()
497 void __iomem *clr; in bgpio_pdev_probe() local
520 clr = bgpio_map(pdev, "clr", sz, &err); in bgpio_pdev_probe()
536 err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags); in bgpio_pdev_probe()
/drivers/staging/media/omap4iss/
Diss.h194 u32 offset, u32 clr) in iss_reg_clr() argument
198 iss_reg_write(iss, res, offset, v & ~clr); in iss_reg_clr()
229 u32 offset, u32 clr, u32 set) in iss_reg_update() argument
233 iss_reg_write(iss, res, offset, (v & ~clr) | set); in iss_reg_update()
/drivers/net/cris/
Deth_v10.c471 IO_STATE(R_IRQ_MASK0_CLR, overrun, clr) | in e100_open()
472 IO_STATE(R_IRQ_MASK0_CLR, underrun, clr) | in e100_open()
473 IO_STATE(R_IRQ_MASK0_CLR, excessive_col, clr); in e100_open()
477 IO_STATE(R_IRQ_MASK2_CLR, dma0_descr, clr) | in e100_open()
478 IO_STATE(R_IRQ_MASK2_CLR, dma0_eop, clr) | in e100_open()
479 IO_STATE(R_IRQ_MASK2_CLR, dma1_descr, clr) | in e100_open()
480 IO_STATE(R_IRQ_MASK2_CLR, dma1_eop, clr); in e100_open()
556 SETS(network_tr_ctrl_shadow, R_NETWORK_TR_CTRL, clr_error, clr); in e100_open()
1201 SETS(network_tr_ctrl_shadow, R_NETWORK_TR_CTRL, clr_error, clr); in e100nw_interrupt()
1215 SETS(network_tr_ctrl_shadow, R_NETWORK_TR_CTRL, clr_error, clr); in e100nw_interrupt()
[all …]
/drivers/irqchip/
Dirq-orion.c56 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in orion_irq_init() local
72 handle_level_irq, clr, 0, in orion_irq_init()
142 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in orion_bridge_irq_init() local
159 handle_edge_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE); in orion_bridge_irq_init()
Dirq-nvic.c55 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in nvic_of_init() local
81 clr, 0, IRQ_GC_INIT_MASK_CACHE); in nvic_of_init()
Dirq-moxart.c64 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in moxart_of_intc_init() local
84 clr, 0, IRQ_GC_INIT_MASK_CACHE); in moxart_of_intc_init()
Dirq-zevio.c78 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in zevio_of_init() local
107 clr, 0, IRQ_GC_INIT_MASK_CACHE); in zevio_of_init()
Dirq-sirfsoc.c36 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in sirfsoc_alloc_gc() local
40 handle_level_irq, clr, set, IRQ_GC_INIT_MASK_CACHE); in sirfsoc_alloc_gc()
Dirq-dw-apb-ictl.c56 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in dw_apb_ictl_init() local
117 np->name, handle_level_irq, clr, 0, in dw_apb_ictl_init()
Dirq-brcmstb-l2.c116 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in brcmstb_l2_intc_of_init() local
153 np->full_name, handle_edge_irq, clr, 0, 0); in brcmstb_l2_intc_of_init()
Dirq-bcm7120-l2.c120 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in bcm7120_l2_intc_of_init() local
175 dn->full_name, handle_level_irq, clr, 0, in bcm7120_l2_intc_of_init()
Dirq-sunxi-nmi.c127 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in sunxi_sc_nmi_irq_init() local
138 handle_fasteoi_irq, clr, 0, in sunxi_sc_nmi_irq_init()
/drivers/i2c/busses/
Di2c-xiic.c328 u32 clr = 0; in xiic_process() local
375 clr = XIIC_INTR_RX_FULL_MASK; in xiic_process()
389 clr |= (isr & XIIC_INTR_TX_ERROR_MASK); in xiic_process()
410 clr = XIIC_INTR_BNB_MASK; in xiic_process()
427 clr = pend & in xiic_process()
463 clr = pend; in xiic_process()
466 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); in xiic_process()
468 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); in xiic_process()
/drivers/video/fbdev/
Dhpfb.c152 u8 clr; in hpfb_fillrect() local
154 clr = region->color & 0xff; in hpfb_fillrect()
160 out_8(fb_regs + TC_WEN, fb_bitmask & clr); in hpfb_fillrect()
164 out_8(fb_regs + TC_WEN, fb_bitmask & ~clr); in hpfb_fillrect()
/drivers/usb/serial/
Dark3116.c473 unsigned set, unsigned clr) in ark3116_tiocmset() argument
492 if (clr & TIOCM_RTS) in ark3116_tiocmset()
494 if (clr & TIOCM_DTR) in ark3116_tiocmset()
496 if (clr & TIOCM_OUT1) in ark3116_tiocmset()
498 if (clr & TIOCM_OUT2) in ark3116_tiocmset()
/drivers/usb/phy/
Dphy-isp1301-omap.c544 u8 set = OTG1_DM_PULLDOWN, clr = OTG1_DM_PULLUP; in otg_update_isp() local
565 clr |= OTG1_DP_PULLDOWN; in otg_update_isp()
576 clr |= OTG1_DP_PULLUP; in otg_update_isp()
582 else clr |= ISP; \ in otg_update_isp()
604 clr |= OTG1_VBUS_DRV; in otg_update_isp()
622 isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, clr); in otg_update_isp()
630 if (clr & OTG1_DP_PULLUP) in otg_update_isp()
636 if (clr & OTG1_DP_PULLUP) in otg_update_isp()
/drivers/gpu/drm/rcar-du/
Drcar_du_crtc.c43 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr) in rcar_du_crtc_clr() argument
48 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr); in rcar_du_crtc_clr()
60 u32 clr, u32 set) in rcar_du_crtc_clr_set() argument
65 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set); in rcar_du_crtc_clr_set()
/drivers/tty/serial/
Dsb1250-duart.c265 unsigned int clr = 0, set = 0, mode2; in sbd_set_mctrl() local
270 clr |= M_DUART_CLR_OPR2; in sbd_set_mctrl()
274 clr |= M_DUART_CLR_OPR0; in sbd_set_mctrl()
275 clr <<= (uport->line) % 2; in sbd_set_mctrl()
285 write_sbdshr(sport, R_DUART_CLEAR_OPR, clr); in sbd_set_mctrl()
/drivers/scsi/aic7xxx/
Daic7xxx.seq79 clr SCSIBUSL;
531 clr SCSIBUSL;
533 clr SCSISIGO;
629 clr CCSCBCTL;
679 clr SCSIBUSL; /* Prevent bit leakage durint SELTO */
694 clr DFCNTRL;
705 clr SCSIRATE;
715 clr A; /* add sizeof(struct scatter) */
726 clr CCSGCTL;
1089 clr HADDR;
[all …]
/drivers/spi/
Dspi-s3c64xx.c913 unsigned int val, clr = 0; in s3c64xx_spi_irq() local
918 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; in s3c64xx_spi_irq()
922 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; in s3c64xx_spi_irq()
926 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; in s3c64xx_spi_irq()
930 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; in s3c64xx_spi_irq()
935 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); in s3c64xx_spi_irq()

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