| /drivers/gpu/drm/radeon/ |
| D | radeon_cp.c | 61 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
63 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off) in radeon_read_ring_rptr() argument
67 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_read_ring_rptr()
68 val = DRM_READ32(dev_priv->ring_rptr, off); in radeon_read_ring_rptr()
71 dev_priv->ring_rptr->handle) + in radeon_read_ring_rptr()
78 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv) in radeon_get_ring_head() argument
80 if (dev_priv->writeback_works) in radeon_get_ring_head()
81 return radeon_read_ring_rptr(dev_priv, 0); in radeon_get_ring_head()
83 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_get_ring_head()
90 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val) in radeon_write_ring_rptr() argument
[all …]
|
| D | r600_cp.c | 102 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) in r600_do_wait_for_fifo() argument
106 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_fifo()
108 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_fifo()
110 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_fifo()
127 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) in r600_do_wait_for_idle() argument
131 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_idle()
133 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_idle()
134 ret = r600_do_wait_for_fifo(dev_priv, 8); in r600_do_wait_for_idle()
136 ret = r600_do_wait_for_fifo(dev_priv, 16); in r600_do_wait_for_idle()
139 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_idle()
[all …]
|
| D | radeon_irq.c | 41 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_irq_set_state() local
44 dev_priv->irq_enable_reg |= mask; in radeon_irq_set_state()
46 dev_priv->irq_enable_reg &= ~mask; in radeon_irq_set_state()
49 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); in radeon_irq_set_state()
54 drm_radeon_private_t *dev_priv = dev->dev_private; in r500_vbl_irq_set_state() local
57 dev_priv->r500_disp_irq_reg |= mask; in r500_vbl_irq_set_state()
59 dev_priv->r500_disp_irq_reg &= ~mask; in r500_vbl_irq_set_state()
62 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); in r500_vbl_irq_set_state()
67 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_enable_vblank() local
69 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) { in radeon_enable_vblank()
[all …]
|
| /drivers/gpu/drm/savage/ |
| D | savage_bci.c | 38 savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n) in savage_bci_wait_fifo_shadow() argument
40 uint32_t mask = dev_priv->status_used_mask; in savage_bci_wait_fifo_shadow()
41 uint32_t threshold = dev_priv->bci_threshold_hi; in savage_bci_wait_fifo_shadow()
46 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold) in savage_bci_wait_fifo_shadow()
53 status = dev_priv->status_ptr[0]; in savage_bci_wait_fifo_shadow()
67 savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n) in savage_bci_wait_fifo_s3d() argument
69 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; in savage_bci_wait_fifo_s3d()
88 savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n) in savage_bci_wait_fifo_s4() argument
90 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; in savage_bci_wait_fifo_s4()
120 savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e) in savage_bci_wait_event_shadow() argument
[all …]
|
| /drivers/gpu/drm/i915/ |
| D | i915_ums.c | 36 struct drm_i915_private *dev_priv = dev->dev_private; in i915_pipe_enabled() local
53 struct drm_i915_private *dev_priv = dev->dev_private; in i915_save_palette() local
65 array = dev_priv->regfile.save_palette_a; in i915_save_palette()
67 array = dev_priv->regfile.save_palette_b; in i915_save_palette()
75 struct drm_i915_private *dev_priv = dev->dev_private; in i915_restore_palette() local
87 array = dev_priv->regfile.save_palette_a; in i915_restore_palette()
89 array = dev_priv->regfile.save_palette_b; in i915_restore_palette()
97 struct drm_i915_private *dev_priv = dev->dev_private; in i915_save_display_reg() local
101 dev_priv->regfile.saveCURACNTR = I915_READ(_CURACNTR); in i915_save_display_reg()
102 dev_priv->regfile.saveCURAPOS = I915_READ(_CURAPOS); in i915_save_display_reg()
[all …]
|
| D | intel_uncore.c | 44 assert_device_not_suspended(struct drm_i915_private *dev_priv) in assert_device_not_suspended() argument
46 WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended, in assert_device_not_suspended()
50 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) in __gen6_gt_wait_for_thread_c0() argument
54 if (IS_HASWELL(dev_priv->dev)) in __gen6_gt_wait_for_thread_c0()
62 …if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_… in __gen6_gt_wait_for_thread_c0()
66 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) in __gen6_gt_force_wake_reset() argument
68 __raw_i915_write32(dev_priv, FORCEWAKE, 0); in __gen6_gt_force_wake_reset()
70 __raw_posting_read(dev_priv, ECOBUS); in __gen6_gt_force_wake_reset()
73 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, in __gen6_gt_force_wake_get() argument
76 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, in __gen6_gt_force_wake_get()
[all …]
|
| D | i915_suspend.c | 34 struct drm_i915_private *dev_priv = dev->dev_private; in i915_read_indexed() local
42 struct drm_i915_private *dev_priv = dev->dev_private; in i915_read_ar() local
51 struct drm_i915_private *dev_priv = dev->dev_private; in i915_write_ar() local
60 struct drm_i915_private *dev_priv = dev->dev_private; in i915_write_indexed() local
68 struct drm_i915_private *dev_priv = dev->dev_private; in i915_save_vga() local
73 dev_priv->regfile.saveVGA0 = I915_READ(VGA0); in i915_save_vga()
74 dev_priv->regfile.saveVGA1 = I915_READ(VGA1); in i915_save_vga()
75 dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD); in i915_save_vga()
76 dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev)); in i915_save_vga()
79 dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK); in i915_save_vga()
[all …]
|
| D | i915_irq.c | 135 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) in ironlake_enable_display_irq() argument
137 assert_spin_locked(&dev_priv->irq_lock); in ironlake_enable_display_irq()
139 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in ironlake_enable_display_irq()
142 if ((dev_priv->irq_mask & mask) != 0) { in ironlake_enable_display_irq()
143 dev_priv->irq_mask &= ~mask; in ironlake_enable_display_irq()
144 I915_WRITE(DEIMR, dev_priv->irq_mask); in ironlake_enable_display_irq()
150 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) in ironlake_disable_display_irq() argument
152 assert_spin_locked(&dev_priv->irq_lock); in ironlake_disable_display_irq()
154 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in ironlake_disable_display_irq()
157 if ((dev_priv->irq_mask & mask) != mask) { in ironlake_disable_display_irq()
[all …]
|
| D | intel_pm.c | 71 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_disable_fbc() local
94 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_enable_fbc() local
102 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE; in i8xx_enable_fbc()
142 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_fbc_enabled() local
150 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_enable_fbc() local
173 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_disable_fbc() local
188 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_fbc_enabled() local
195 struct drm_i915_private *dev_priv = dev->dev_private; in sandybridge_blit_fbc_update() local
202 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA); in sandybridge_blit_fbc_update()
215 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA); in sandybridge_blit_fbc_update()
[all …]
|
| D | i915_dma.c | 56 intel_ring_begin(LP_RING(dev_priv), (n))
59 intel_ring_emit(LP_RING(dev_priv), x)
62 __intel_ring_advance(LP_RING(dev_priv))
76 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg) in intel_read_legacy_status_page() argument
78 if (I915_NEED_GFX_HWS(dev_priv->dev)) in intel_read_legacy_status_page()
79 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg); in intel_read_legacy_status_page()
81 return intel_read_status_page(LP_RING(dev_priv), reg); in intel_read_legacy_status_page()
84 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg) argument
85 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) argument
90 struct drm_i915_private *dev_priv = dev->dev_private; in i915_update_dri1_breadcrumb() local
[all …]
|
| D | intel_sideband.c | 42 static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, in vlv_sideband_rw() argument
52 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); in vlv_sideband_rw()
78 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr) in vlv_punit_read() argument
82 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in vlv_punit_read()
84 mutex_lock(&dev_priv->dpio_lock); in vlv_punit_read()
85 vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT, in vlv_punit_read()
87 mutex_unlock(&dev_priv->dpio_lock); in vlv_punit_read()
92 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val) in vlv_punit_write() argument
94 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in vlv_punit_write()
96 mutex_lock(&dev_priv->dpio_lock); in vlv_punit_write()
[all …]
|
| D | intel_bios.c | 210 parse_lfp_panel_data(struct drm_i915_private *dev_priv, in parse_lfp_panel_data() argument
225 dev_priv->vbt.lvds_dither = lvds_options->pixel_dither; in parse_lfp_panel_data()
240 dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT; in parse_lfp_panel_data()
244 dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT; in parse_lfp_panel_data()
248 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; in parse_lfp_panel_data()
261 dev_priv->vbt.lvds_vbt = 1; in parse_lfp_panel_data()
273 dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; in parse_lfp_panel_data()
295 dev_priv->lvds_downclock_avail = 1; in parse_lfp_panel_data()
296 dev_priv->lvds_downclock = downclock * 10; in parse_lfp_panel_data()
309 dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val; in parse_lfp_panel_data()
[all …]
|
| D | intel_i2c.c | 64 struct drm_i915_private *dev_priv = dev->dev_private; in intel_i2c_reset() local
66 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); in intel_i2c_reset()
67 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); in intel_i2c_reset()
70 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) in intel_i2c_quirk_set() argument
75 if (!IS_PINEVIEW(dev_priv->dev)) in intel_i2c_quirk_set()
88 struct drm_i915_private *dev_priv = bus->dev_priv; in get_reserved() local
89 struct drm_device *dev = dev_priv->dev; in get_reserved()
104 struct drm_i915_private *dev_priv = bus->dev_priv; in get_clock() local
114 struct drm_i915_private *dev_priv = bus->dev_priv; in get_data() local
124 struct drm_i915_private *dev_priv = bus->dev_priv; in set_clock() local
[all …]
|
| /drivers/gpu/drm/vmwgfx/ |
| D | vmwgfx_irq.c | 36 struct vmw_private *dev_priv = vmw_priv(dev); in vmw_irq_handler() local
39 spin_lock(&dev_priv->irq_lock); in vmw_irq_handler()
40 status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); in vmw_irq_handler()
41 masked_status = status & dev_priv->irq_mask; in vmw_irq_handler()
42 spin_unlock(&dev_priv->irq_lock); in vmw_irq_handler()
45 outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); in vmw_irq_handler()
52 vmw_fences_update(dev_priv->fman); in vmw_irq_handler()
53 wake_up_all(&dev_priv->fence_queue); in vmw_irq_handler()
57 wake_up_all(&dev_priv->fifo_queue); in vmw_irq_handler()
63 static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno) in vmw_fifo_idle() argument
[all …]
|
| D | vmwgfx_drv.c | 297 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) in vmw_dummy_query_bo_create() argument
310 ret = ttm_bo_create(&dev_priv->bdev, in vmw_dummy_query_bo_create()
338 dev_priv->dummy_query_bo = bo; in vmw_dummy_query_bo_create()
343 static int vmw_request_device(struct vmw_private *dev_priv) in vmw_request_device() argument
347 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); in vmw_request_device()
352 vmw_fence_fifo_up(dev_priv->fman); in vmw_request_device()
353 if (dev_priv->has_mob) { in vmw_request_device()
354 ret = vmw_otables_setup(dev_priv); in vmw_request_device()
361 ret = vmw_dummy_query_bo_create(dev_priv); in vmw_request_device()
368 if (dev_priv->has_mob) in vmw_request_device()
[all …]
|
| D | vmwgfx_fifo.c | 32 bool vmw_fifo_have_3d(struct vmw_private *dev_priv) in vmw_fifo_have_3d() argument
34 __le32 __iomem *fifo_mem = dev_priv->mmio_virt; in vmw_fifo_have_3d()
36 const struct vmw_fifo_state *fifo = &dev_priv->fifo; in vmw_fifo_have_3d()
38 if (!(dev_priv->capabilities & SVGA_CAP_3D)) in vmw_fifo_have_3d()
41 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { in vmw_fifo_have_3d()
44 if (!dev_priv->has_mob) in vmw_fifo_have_3d()
47 spin_lock(&dev_priv->cap_lock); in vmw_fifo_have_3d()
48 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D); in vmw_fifo_have_3d()
49 result = vmw_read(dev_priv, SVGA_REG_DEV_CAP); in vmw_fifo_have_3d()
50 spin_unlock(&dev_priv->cap_lock); in vmw_fifo_have_3d()
[all …]
|
| /drivers/gpu/drm/via/ |
| D | via_dma.c | 60 dev_priv->dma_low += 8; \
68 dev_priv->dma_low += 8; \
71 static void via_cmdbuf_start(drm_via_private_t *dev_priv);
72 static void via_cmdbuf_pause(drm_via_private_t *dev_priv);
73 static void via_cmdbuf_reset(drm_via_private_t *dev_priv);
74 static void via_cmdbuf_rewind(drm_via_private_t *dev_priv);
75 static int via_wait_idle(drm_via_private_t *dev_priv);
76 static void via_pad_cache(drm_via_private_t *dev_priv, int qwords);
82 static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv) in via_cmdbuf_space() argument
84 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; in via_cmdbuf_space()
[all …]
|
| D | via_irq.c | 100 drm_via_private_t *dev_priv = dev->dev_private; in via_get_vblank_counter() local
104 return atomic_read(&dev_priv->vbl_received); in via_get_vblank_counter()
110 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; in via_driver_irq_handler() local
114 drm_via_irq_t *cur_irq = dev_priv->via_irqs; in via_driver_irq_handler()
119 atomic_inc(&dev_priv->vbl_received); in via_driver_irq_handler()
120 if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) { in via_driver_irq_handler()
122 if (dev_priv->last_vblank_valid) { in via_driver_irq_handler()
123 dev_priv->usec_per_vblank = in via_driver_irq_handler()
125 &dev_priv->last_vblank) >> 4; in via_driver_irq_handler()
127 dev_priv->last_vblank = cur_vblank; in via_driver_irq_handler()
[all …]
|
| /drivers/gpu/drm/r128/ |
| D | r128_cce.c | 49 drm_r128_private_t *dev_priv = dev->dev_private; in R128_READ_PLL() local
56 static void r128_status(drm_r128_private_t *dev_priv) in r128_status() argument
77 static int r128_do_pixcache_flush(drm_r128_private_t *dev_priv) in r128_do_pixcache_flush() argument
85 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_pixcache_flush()
97 static int r128_do_wait_for_fifo(drm_r128_private_t *dev_priv, int entries) in r128_do_wait_for_fifo() argument
101 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_wait_for_fifo()
114 static int r128_do_wait_for_idle(drm_r128_private_t *dev_priv) in r128_do_wait_for_idle() argument
118 ret = r128_do_wait_for_fifo(dev_priv, 64); in r128_do_wait_for_idle()
122 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_wait_for_idle()
124 r128_do_pixcache_flush(dev_priv); in r128_do_wait_for_idle()
[all …]
|
| /drivers/gpu/drm/mga/ |
| D | mga_dma.c | 53 int mga_do_wait_for_idle(drm_mga_private_t *dev_priv) in mga_do_wait_for_idle() argument
59 for (i = 0; i < dev_priv->usec_timeout; i++) { in mga_do_wait_for_idle()
75 static int mga_do_dma_reset(drm_mga_private_t *dev_priv) in mga_do_dma_reset() argument
77 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_do_dma_reset()
78 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_reset()
103 void mga_do_dma_flush(drm_mga_private_t *dev_priv) in mga_do_dma_flush() argument
105 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_flush()
113 for (i = 0; i < dev_priv->usec_timeout; i++) { in mga_do_dma_flush()
125 tail = primary->tail + dev_priv->primary->offset; in mga_do_dma_flush()
148 DRM_DEBUG(" head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset)); in mga_do_dma_flush()
[all …]
|
| /drivers/gpu/drm/gma500/ |
| D | psb_irq.c | 86 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) in psb_enable_pipestat() argument
88 if ((dev_priv->pipestat[pipe] & mask) != mask) { in psb_enable_pipestat()
90 dev_priv->pipestat[pipe] |= mask; in psb_enable_pipestat()
92 if (gma_power_begin(dev_priv->dev, false)) { in psb_enable_pipestat()
97 gma_power_end(dev_priv->dev); in psb_enable_pipestat()
103 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) in psb_disable_pipestat() argument
105 if ((dev_priv->pipestat[pipe] & mask) != 0) { in psb_disable_pipestat()
107 dev_priv->pipestat[pipe] &= ~mask; in psb_disable_pipestat()
108 if (gma_power_begin(dev_priv->dev, false)) { in psb_disable_pipestat()
113 gma_power_end(dev_priv->dev); in psb_disable_pipestat()
[all …]
|
| D | psb_drv.c | 112 struct drm_psb_private *dev_priv = dev->dev_private; in psb_driver_lastclose() local
113 struct psb_fbdev *fbdev = dev_priv->fbdev; in psb_driver_lastclose()
124 struct drm_psb_private *dev_priv = dev->dev_private; in psb_do_init() local
125 struct psb_gtt *pg = &dev_priv->gtt; in psb_do_init()
138 dev_priv->gatt_free_offset = pg->mmu_gatt_start + in psb_do_init()
141 spin_lock_init(&dev_priv->irqmask_lock); in psb_do_init()
142 spin_lock_init(&dev_priv->lock_2d); in psb_do_init()
153 psb_spank(dev_priv); in psb_do_init()
164 struct drm_psb_private *dev_priv = dev->dev_private; in psb_driver_unload() local
168 if (dev_priv) { in psb_driver_unload()
[all …]
|
| D | intel_bios.c | 58 parse_edp(struct drm_psb_private *dev_priv, struct bdb_header *bdb) in parse_edp() argument
67 dev_priv->edp.bpp = 18; in parse_edp()
69 if (dev_priv->edp.support) { in parse_edp()
71 dev_priv->edp.bpp); in parse_edp()
76 panel_type = dev_priv->panel_type; in parse_edp()
79 dev_priv->edp.bpp = 18; in parse_edp()
82 dev_priv->edp.bpp = 24; in parse_edp()
85 dev_priv->edp.bpp = 30; in parse_edp()
93 dev_priv->edp.pps = *edp_pps; in parse_edp()
96 dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8, in parse_edp()
[all …]
|
| D | power.c | 49 struct drm_psb_private *dev_priv = dev->dev_private; in gma_power_init() local
52 dev_priv->apm_base = dev_priv->apm_reg & 0xffff; in gma_power_init()
53 dev_priv->ospm_base &= 0xffff; in gma_power_init()
55 dev_priv->display_power = true; /* We start active */ in gma_power_init()
56 dev_priv->display_count = 0; /* Currently no users */ in gma_power_init()
57 dev_priv->suspended = false; /* And not suspended */ in gma_power_init()
61 if (dev_priv->ops->init_pm) in gma_power_init()
62 dev_priv->ops->init_pm(dev); in gma_power_init()
85 struct drm_psb_private *dev_priv = dev->dev_private; in gma_suspend_display() local
87 if (dev_priv->suspended) in gma_suspend_display()
[all …]
|
| /drivers/gpu/drm/i810/ |
| D | i810_dma.c | 91 drm_i810_private_t *dev_priv; in i810_mmap_buffers() local
96 dev_priv = dev->dev_private; in i810_mmap_buffers()
97 buf = dev_priv->mmap_buffer; in i810_mmap_buffers()
126 drm_i810_private_t *dev_priv = dev->dev_private; in i810_map_buffer() local
136 dev_priv->mmap_buffer = buf; in i810_map_buffer()
140 dev_priv->mmap_buffer = NULL; in i810_map_buffer()
212 drm_i810_private_t *dev_priv = in i810_dma_cleanup() local
215 if (dev_priv->ring.virtual_start) in i810_dma_cleanup()
216 drm_legacy_ioremapfree(&dev_priv->ring.map, dev); in i810_dma_cleanup()
217 if (dev_priv->hw_status_page) { in i810_dma_cleanup()
[all …]
|