| /drivers/gpu/drm/i915/ |
| D | intel_dp_mst.c | 33 struct intel_crtc_config *pipe_config) in intel_dp_mst_compute_config() argument
41 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; in intel_dp_mst_compute_config()
45 pipe_config->dp_encoder_is_mst = true; in intel_dp_mst_compute_config()
46 pipe_config->has_pch_encoder = false; in intel_dp_mst_compute_config()
47 pipe_config->has_dp_encoder = true; in intel_dp_mst_compute_config()
57 pipe_config->pipe_bpp = 24; in intel_dp_mst_compute_config()
58 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); in intel_dp_mst_compute_config()
74 pipe_config->pbn = mst_pbn; in intel_dp_mst_compute_config()
79 pipe_config->port_clock, in intel_dp_mst_compute_config()
80 &pipe_config->dp_m_n); in intel_dp_mst_compute_config()
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| D | intel_panel.c | 101 struct intel_crtc_config *pipe_config, in intel_pch_panel_fitting() argument
107 adjusted_mode = &pipe_config->adjusted_mode; in intel_pch_panel_fitting()
112 if (adjusted_mode->hdisplay == pipe_config->pipe_src_w && in intel_pch_panel_fitting()
113 adjusted_mode->vdisplay == pipe_config->pipe_src_h) in intel_pch_panel_fitting()
118 width = pipe_config->pipe_src_w; in intel_pch_panel_fitting()
119 height = pipe_config->pipe_src_h; in intel_pch_panel_fitting()
128 * pipe_config->pipe_src_h; in intel_pch_panel_fitting()
129 u32 scaled_height = pipe_config->pipe_src_w in intel_pch_panel_fitting()
132 width = scaled_height / pipe_config->pipe_src_h; in intel_pch_panel_fitting()
139 height = scaled_width / pipe_config->pipe_src_w; in intel_pch_panel_fitting()
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| D | intel_ddi.c | 617 struct intel_crtc_config *pipe_config) in hsw_ddi_clock_get() argument
623 val = pipe_config->ddi_pll_sel; in hsw_ddi_clock_get()
658 pipe_config->port_clock = link_clock * 2; in hsw_ddi_clock_get()
660 if (pipe_config->has_pch_encoder) in hsw_ddi_clock_get()
661 pipe_config->adjusted_mode.crtc_clock = in hsw_ddi_clock_get()
662 intel_dotclock_calculate(pipe_config->port_clock, in hsw_ddi_clock_get()
663 &pipe_config->fdi_m_n); in hsw_ddi_clock_get()
664 else if (pipe_config->has_dp_encoder) in hsw_ddi_clock_get()
665 pipe_config->adjusted_mode.crtc_clock = in hsw_ddi_clock_get()
666 intel_dotclock_calculate(pipe_config->port_clock, in hsw_ddi_clock_get()
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| D | intel_display.c | 81 struct intel_crtc_config *pipe_config);
83 struct intel_crtc_config *pipe_config);
4428 struct intel_crtc_config *pipe_config = &crtc->config; in i9xx_pfit_enable() local
4440 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); in i9xx_pfit_enable()
4441 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); in i9xx_pfit_enable()
5219 struct intel_crtc_config *pipe_config) in ironlake_check_fdi_lanes() argument
5226 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
5227 if (pipe_config->fdi_lanes > 4) { in ironlake_check_fdi_lanes()
5229 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
5234 if (pipe_config->fdi_lanes > 2) { in ironlake_check_fdi_lanes()
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| D | intel_crt.c | 113 struct intel_crtc_config *pipe_config) in intel_crt_get_config() argument
118 pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); in intel_crt_get_config()
120 dotclock = pipe_config->port_clock; in intel_crt_get_config()
123 ironlake_check_encoder_dotclock(pipe_config, dotclock); in intel_crt_get_config()
125 pipe_config->adjusted_mode.crtc_clock = dotclock; in intel_crt_get_config()
129 struct intel_crtc_config *pipe_config) in hsw_crt_get_config() argument
131 intel_ddi_get_config(encoder, pipe_config); in hsw_crt_get_config()
133 pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | in hsw_crt_get_config()
137 pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); in hsw_crt_get_config()
306 struct intel_crtc_config *pipe_config) in intel_crt_compute_config() argument
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| D | intel_lvds.c | 96 struct intel_crtc_config *pipe_config) in intel_lvds_get_config() argument
118 pipe_config->adjusted_mode.flags |= flags; in intel_lvds_get_config()
124 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; in intel_lvds_get_config()
127 dotclock = pipe_config->port_clock; in intel_lvds_get_config()
130 ironlake_check_encoder_dotclock(pipe_config, dotclock); in intel_lvds_get_config()
132 pipe_config->adjusted_mode.crtc_clock = dotclock; in intel_lvds_get_config()
280 struct intel_crtc_config *pipe_config) in intel_lvds_compute_config() argument
287 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; in intel_lvds_compute_config()
302 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { in intel_lvds_compute_config()
304 pipe_config->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
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| D | intel_hdmi.c | 712 struct intel_crtc_config *pipe_config) in intel_hdmi_get_config() argument
733 pipe_config->has_hdmi_sink = true; in intel_hdmi_get_config()
736 pipe_config->has_audio = true; in intel_hdmi_get_config()
740 pipe_config->limited_color_range = true; in intel_hdmi_get_config()
742 pipe_config->adjusted_mode.flags |= flags; in intel_hdmi_get_config()
745 dotclock = pipe_config->port_clock * 2 / 3; in intel_hdmi_get_config()
747 dotclock = pipe_config->port_clock; in intel_hdmi_get_config()
750 ironlake_check_encoder_dotclock(pipe_config, dotclock); in intel_hdmi_get_config()
752 pipe_config->adjusted_mode.crtc_clock = dotclock; in intel_hdmi_get_config()
914 struct intel_crtc_config *pipe_config) in intel_hdmi_compute_config() argument
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| D | intel_sdvo.c | 1088 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config) in i9xx_adjust_sdvo_tv_clock() argument
1090 unsigned dotclock = pipe_config->port_clock; in i9xx_adjust_sdvo_tv_clock()
1091 struct dpll *clock = &pipe_config->dpll; in i9xx_adjust_sdvo_tv_clock()
1111 pipe_config->clock_set = true; in i9xx_adjust_sdvo_tv_clock()
1115 struct intel_crtc_config *pipe_config) in intel_sdvo_compute_config() argument
1118 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; in intel_sdvo_compute_config()
1119 struct drm_display_mode *mode = &pipe_config->requested_mode; in intel_sdvo_compute_config()
1122 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()
1125 pipe_config->has_pch_encoder = true; in intel_sdvo_compute_config()
1139 pipe_config->sdvo_tv_clock = true; in intel_sdvo_compute_config()
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| D | intel_dvo.c | 147 struct intel_crtc_config *pipe_config) in intel_dvo_get_config() argument
163 pipe_config->adjusted_mode.flags |= flags; in intel_dvo_get_config()
165 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
264 struct intel_crtc_config *pipe_config) in intel_dvo_compute_config() argument
267 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; in intel_dvo_compute_config()
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| D | intel_drv.h | 159 struct intel_crtc_config *pipe_config);
788 struct intel_crtc_config *pipe_config);
792 struct intel_crtc_config *pipe_config);
902 struct intel_crtc_config *pipe_config);
906 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
915 struct intel_crtc_config *pipe_config);
934 struct intel_crtc_config *pipe_config);
1007 struct intel_crtc_config *pipe_config);
1041 struct intel_crtc_config *pipe_config,
1044 struct intel_crtc_config *pipe_config,
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| D | intel_dp.c | 965 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw) in hsw_dp_set_ddi_pll_sel() argument
969 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; in hsw_dp_set_ddi_pll_sel()
972 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; in hsw_dp_set_ddi_pll_sel()
975 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; in hsw_dp_set_ddi_pll_sel()
982 struct intel_crtc_config *pipe_config, int link_bw) in intel_dp_set_clock() argument
1005 pipe_config->dpll = divisor[i].dpll; in intel_dp_set_clock()
1006 pipe_config->clock_set = true; in intel_dp_set_clock()
1015 struct intel_crtc_config *pipe_config) in intel_dp_compute_config() argument
1019 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; in intel_dp_compute_config()
1035 pipe_config->has_pch_encoder = true; in intel_dp_compute_config()
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| D | intel_dsi.c | 367 struct intel_crtc_config *pipe_config) in intel_dsi_get_config() argument
376 pipe_config->dpll_hw_state.dpll_md = 0; in intel_dsi_get_config()
378 pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); in intel_dsi_get_config()
382 pipe_config->adjusted_mode.crtc_clock = pclk; in intel_dsi_get_config()
383 pipe_config->port_clock = pclk; in intel_dsi_get_config()
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| D | intel_tv.c | 911 struct intel_crtc_config *pipe_config) in intel_tv_get_config() argument
913 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_tv_get_config()
918 struct intel_crtc_config *pipe_config) in intel_tv_compute_config() argument
926 pipe_config->adjusted_mode.crtc_clock = tv_mode->clock; in intel_tv_compute_config()
928 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
931 pipe_config->adjusted_mode.flags = 0; in intel_tv_compute_config()
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| /drivers/gpu/drm/radeon/ |
| D | atombios_crtc.c | 1335 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; in dce4_crtc_do_set_base() local
1337 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config); in dce4_crtc_do_set_base()
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