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Searched refs:writel_relaxed (Results 1 – 25 of 146) sorted by relevance

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/drivers/phy/
Dphy-qcom-apq8064-sata.c104 writel_relaxed(0x01, base + SATA_PHY_SER_CTRL); in qcom_apq8064_sata_phy_init()
105 writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0); in qcom_apq8064_sata_phy_init()
110 writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0); in qcom_apq8064_sata_phy_init()
111 writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1); in qcom_apq8064_sata_phy_init()
112 writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0); in qcom_apq8064_sata_phy_init()
113 writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0); in qcom_apq8064_sata_phy_init()
114 writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2); in qcom_apq8064_sata_phy_init()
117 writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG); in qcom_apq8064_sata_phy_init()
118 writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG); in qcom_apq8064_sata_phy_init()
120 writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0); in qcom_apq8064_sata_phy_init()
[all …]
/drivers/crypto/ux500/cryp/
Dcryp.c147 writel_relaxed(cr_for_kse, &device_data->base->cr); in cryp_set_configuration()
218 writel_relaxed(key_value.key_value_left, in cryp_configure_key_values()
220 writel_relaxed(key_value.key_value_right, in cryp_configure_key_values()
224 writel_relaxed(key_value.key_value_left, in cryp_configure_key_values()
226 writel_relaxed(key_value.key_value_right, in cryp_configure_key_values()
230 writel_relaxed(key_value.key_value_left, in cryp_configure_key_values()
232 writel_relaxed(key_value.key_value_right, in cryp_configure_key_values()
236 writel_relaxed(key_value.key_value_left, in cryp_configure_key_values()
238 writel_relaxed(key_value.key_value_right, in cryp_configure_key_values()
265 writel_relaxed(init_vector_value.init_value_left, in cryp_configure_init_vector()
[all …]
/drivers/clocksource/
Dtimer-marco.c59 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7, in sirfsoc_timer_count_disable()
66 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3, in sirfsoc_timer_count_enable()
77 writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); in sirfsoc_timer_interrupt()
92 writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | in sirfsoc_timer_read()
109 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 + in sirfsoc_timer_set_next_event()
111 writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 + in sirfsoc_timer_set_next_event()
147 writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); in sirfsoc_clocksource_resume()
149 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], in sirfsoc_clocksource_resume()
151 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], in sirfsoc_clocksource_resume()
154 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | in sirfsoc_clocksource_resume()
[all …]
Dtimer-prima2.c68 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); in sirfsoc_timer_interrupt()
81 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, in sirfsoc_timer_read()
95 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, in sirfsoc_timer_set_next_event()
99 writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0); in sirfsoc_timer_set_next_event()
100 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, in sirfsoc_timer_set_next_event()
116 writel_relaxed(val | BIT(0), in sirfsoc_timer_set_mode()
120 writel_relaxed(val & ~BIT(0), in sirfsoc_timer_set_mode()
133 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, in sirfsoc_clocksource_suspend()
147 writel_relaxed(sirfsoc_timer_reg_val[i], in sirfsoc_clocksource_resume()
150 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], in sirfsoc_clocksource_resume()
[all …]
Dtime-efm32.c59 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_mode()
60 writel_relaxed(ddata->periodic_top, ddata->base + TIMERn_TOP); in efm32_clock_event_set_mode()
61 writel_relaxed(TIMERn_CTRL_PRESC_1024 | in efm32_clock_event_set_mode()
65 writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD); in efm32_clock_event_set_mode()
69 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_mode()
70 writel_relaxed(TIMERn_CTRL_PRESC_1024 | in efm32_clock_event_set_mode()
79 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_mode()
93 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_next_event()
94 writel_relaxed(evt, ddata->base + TIMERn_CNT); in efm32_clock_event_set_next_event()
95 writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD); in efm32_clock_event_set_next_event()
[all …]
Dcadence_ttc_timer.c123 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
125 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); in ttc_set_interval()
133 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
217 writel_relaxed(ctrl_reg, in ttc_set_mode()
224 writel_relaxed(ctrl_reg, in ttc_set_mode()
294 writel_relaxed(ttccs->scale_clk_ctrl_reg_new, in ttc_rate_change_clocksource_cb()
304 writel_relaxed(ttccs->scale_clk_ctrl_reg_new, in ttc_rate_change_clocksource_cb()
314 writel_relaxed(ttccs->scale_clk_ctrl_reg_old, in ttc_rate_change_clocksource_cb()
363 writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET); in ttc_setup_clocksource()
364 writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, in ttc_setup_clocksource()
[all …]
/drivers/mmc/host/
Dmmci_qcom_dml.c68 writel_relaxed(config, base + DML_CONFIG); in dml_start_xfer()
71 writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE); in dml_start_xfer()
74 writel_relaxed(data->blocks * data->blksz, in dml_start_xfer()
79 writel_relaxed(config, base + DML_CONFIG); in dml_start_xfer()
81 writel_relaxed(1, base + DML_PRODUCER_START); in dml_start_xfer()
88 writel_relaxed(config, base + DML_CONFIG); in dml_start_xfer()
92 writel_relaxed(config, base + DML_CONFIG); in dml_start_xfer()
94 writel_relaxed(1, base + DML_CONSUMER_START); in dml_start_xfer()
137 writel_relaxed(1, base + DML_SW_RESET); in dml_hw_init()
158 writel_relaxed(config, base + DML_CONFIG); in dml_hw_init()
[all …]
/drivers/video/fbdev/mmp/hw/
Dmmp_ctrl.c55 writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR); in ctrl_handle_irq()
139 writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); in dmafetch_set_fmt()
152 writel_relaxed(win->pitch[0], &regs->v_pitch_yc); in overlay_set_win()
153 writel_relaxed(win->pitch[2] << 16 | in overlay_set_win()
156 writel_relaxed((win->ysrc << 16) | win->xsrc, &regs->v_size); in overlay_set_win()
157 writel_relaxed((win->ydst << 16) | win->xdst, &regs->v_size_z); in overlay_set_win()
158 writel_relaxed(win->ypos << 16 | win->xpos, &regs->v_start); in overlay_set_win()
160 writel_relaxed(win->pitch[0], &regs->g_pitch); in overlay_set_win()
162 writel_relaxed((win->ysrc << 16) | win->xsrc, &regs->g_size); in overlay_set_win()
163 writel_relaxed((win->ydst << 16) | win->xdst, &regs->g_size_z); in overlay_set_win()
[all …]
Dmmp_spi.c51 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); in lcd_spi_write()
55 writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
58 writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
61 writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
87 writel_relaxed(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
89 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); in lcd_spi_write()
113 writel_relaxed(IOPAD_DUMB18SPI | in lcd_spi_setup()
/drivers/net/ethernet/hisilicon/
Dhix5hd2_gmac.c265 writel_relaxed(val, priv->ctrl_base); in hix5hd2_config_port()
267 writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN); in hix5hd2_config_port()
274 writel_relaxed(val, priv->base + PORT_MODE); in hix5hd2_config_port()
275 writel_relaxed(0, priv->base + MODE_CHANGE_EN); in hix5hd2_config_port()
276 writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL); in hix5hd2_config_port()
281 writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN); in hix5hd2_set_desc_depth()
282 writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH); in hix5hd2_set_desc_depth()
283 writel_relaxed(0, priv->base + RX_FQ_REG_EN); in hix5hd2_set_desc_depth()
285 writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN); in hix5hd2_set_desc_depth()
286 writel_relaxed(rx << 3, priv->base + RX_BQ_DEPTH); in hix5hd2_set_desc_depth()
[all …]
/drivers/irqchip/
Dirq-gic-common.c49 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); in gic_configure_irq()
59 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); in gic_configure_irq()
62 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); in gic_configure_irq()
77 writel_relaxed(GICD_INT_ACTLOW_LVLTRIG, in gic_dist_config()
84 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i); in gic_dist_config()
91 writel_relaxed(GICD_INT_EN_CLR_X32, in gic_dist_config()
106 writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR); in gic_cpu_config()
107 writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET); in gic_cpu_config()
113 writel_relaxed(GICD_INT_DEF_PRI_X4, in gic_cpu_config()
Dirq-sirfsoc.c72 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0); in sirfsoc_irq_init()
73 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1); in sirfsoc_irq_init()
75 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0); in sirfsoc_irq_init()
76 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1); in sirfsoc_irq_init()
109 writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0); in sirfsoc_irq_resume()
110 writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1); in sirfsoc_irq_resume()
111 writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0); in sirfsoc_irq_resume()
112 writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1); in sirfsoc_irq_resume()
Dirq-gic.c159 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); in gic_mask_irq()
172 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); in gic_unmask_irq()
184 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); in gic_eoi_irq()
240 writel_relaxed(val | bit, reg); in gic_set_affinity()
277 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); in gic_handle_irq()
374 writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); in gic_cpu_if_up()
385 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); in gic_dist_init()
394 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); in gic_dist_init()
398 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); in gic_dist_init()
425 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); in gic_cpu_init()
[all …]
Dirq-hip04.c99 writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_CLEAR + in hip04_mask_irq()
109 writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_SET + in hip04_unmask_irq()
116 writel_relaxed(hip04_irq(d), hip04_cpu_base(d) + GIC_CPU_EOI); in hip04_eoi_irq()
162 writel_relaxed(val | bit, reg); in hip04_irq_set_affinity()
184 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); in hip04_handle_irq()
230 writel_relaxed(0, base + GIC_DIST_CTRL); in hip04_irq_dist_init()
238 writel_relaxed(cpumask, base + GIC_DIST_TARGET + ((i * 2) & ~3)); in hip04_irq_dist_init()
242 writel_relaxed(1, base + GIC_DIST_CTRL); in hip04_irq_dist_init()
269 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); in hip04_irq_cpu_init()
270 writel_relaxed(1, base + GIC_CPU_CTRL); in hip04_irq_cpu_init()
[all …]
/drivers/spi/
Dspi-qup.c181 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
182 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
186 writel_relaxed(cur_state, controller->base + QUP_STATE); in spi_qup_set_state()
265 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); in spi_qup_fifo_write()
286 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
287 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
288 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
372 writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
373 writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
375 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
[all …]
/drivers/soc/ti/
Dknav_dma.c156 writel_relaxed(v, &chan->reg_chan->mode); in chan_start()
157 writel_relaxed(DMA_ENABLE, &chan->reg_chan->control); in chan_start()
161 writel_relaxed(cfg->u.tx.priority, &chan->reg_tx_sched->prio); in chan_start()
179 writel_relaxed(v, &chan->reg_rx_flow->control); in chan_start()
180 writel_relaxed(0, &chan->reg_rx_flow->tags); in chan_start()
181 writel_relaxed(0, &chan->reg_rx_flow->tag_sel); in chan_start()
185 writel_relaxed(v, &chan->reg_rx_flow->fdq_sel[0]); in chan_start()
189 writel_relaxed(v, &chan->reg_rx_flow->fdq_sel[1]); in chan_start()
191 writel_relaxed(0, &chan->reg_rx_flow->thresh[0]); in chan_start()
192 writel_relaxed(0, &chan->reg_rx_flow->thresh[1]); in chan_start()
[all …]
/drivers/i2c/busses/
Di2c-st.c201 writel_relaxed(readl_relaxed(reg) | mask, reg); in st_i2c_set_bits()
206 writel_relaxed(readl_relaxed(reg) & ~mask, reg); in st_i2c_clr_bits()
282 writel_relaxed(val, i2c_dev->base + SSC_CLR); in st_i2c_hw_config()
286 writel_relaxed(val, i2c_dev->base + SSC_CTL); in st_i2c_hw_config()
293 writel_relaxed(val, i2c_dev->base + SSC_BRG); in st_i2c_hw_config()
296 writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG); in st_i2c_hw_config()
299 writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C); in st_i2c_hw_config()
303 writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD); in st_i2c_hw_config()
307 writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP); in st_i2c_hw_config()
311 writel_relaxed(val, i2c_dev->base + SSC_START_HOLD); in st_i2c_hw_config()
[all …]
Di2c-hix5hd2.c106 writel_relaxed(val, priv->regs + HIX5I2C_ICR); in hix5hd2_i2c_clr_pend_irq()
113 writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR); in hix5hd2_i2c_clr_all_irq()
118 writel_relaxed(0, priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_disable_irq()
123 writel_relaxed(I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL, in hix5hd2_i2c_enable_irq()
134 writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_drv_setrate()
139 writel_relaxed(scl, priv->regs + HIX5I2C_SCL_H); in hix5hd2_i2c_drv_setrate()
140 writel_relaxed(scl, priv->regs + HIX5I2C_SCL_L); in hix5hd2_i2c_drv_setrate()
143 writel_relaxed(val, priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_drv_setrate()
198 writel_relaxed(I2C_STOP, priv->regs + HIX5I2C_COM); in hix5hd2_rw_handle_stop()
208 writel_relaxed(I2C_READ | I2C_NO_ACK, priv->regs + HIX5I2C_COM); in hix5hd2_read_handle()
[all …]
/drivers/gpio/
Dgpio-mvebu.c196 writel_relaxed(u, mvebu_gpioreg_out(mvchip)); in mvebu_gpio_set()
229 writel_relaxed(u, mvebu_gpioreg_blink(mvchip)); in mvebu_gpio_blink()
250 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); in mvebu_gpio_direction_input()
277 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); in mvebu_gpio_direction_output()
300 writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip)); in mvebu_gpio_irq_ack()
314 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip)); in mvebu_gpio_edge_irq_mask()
328 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip)); in mvebu_gpio_edge_irq_unmask()
342 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip)); in mvebu_gpio_level_irq_mask()
356 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip)); in mvebu_gpio_level_irq_unmask()
418 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); in mvebu_gpio_irq_set_type()
[all …]
Dgpio-pxa.c236 writel_relaxed(value, base + GPDR_OFFSET); in pxa_gpio_direction_input()
249 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); in pxa_gpio_direction_output()
258 writel_relaxed(tmp, base + GPDR_OFFSET); in pxa_gpio_direction_output()
272 writel_relaxed(1 << offset, gpio_chip_base(chip) + in pxa_gpio_set()
346 writel_relaxed(grer, c->regbase + GRER_OFFSET); in update_edge_detect()
347 writel_relaxed(gfer, c->regbase + GFER_OFFSET); in update_edge_detect()
374 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type()
376 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type()
412 writel_relaxed(gedr, c->regbase + GEDR_OFFSET); in pxa_gpio_demux_handler()
430 writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); in pxa_ack_muxed_gpio()
[all …]
Dgpio-omap.c114 writel_relaxed(l, reg); in omap_set_gpio_direction()
134 writel_relaxed(l, reg); in omap_set_gpio_dataout_reg()
150 writel_relaxed(l, reg); in omap_set_gpio_dataout_mask()
177 writel_relaxed(l, base + reg); in omap_gpio_rmw()
186 writel_relaxed(bank->dbck_enable_mask, in omap_gpio_dbck_enable()
199 writel_relaxed(0, bank->base + bank->regs->debounce_en); in omap_gpio_dbck_disable()
236 writel_relaxed(debounce, reg); in omap2_set_gpio_debounce()
247 writel_relaxed(val, reg); in omap2_set_gpio_debounce()
286 writel_relaxed(bank->context.debounce_en, in omap_clear_gpio_debounce()
291 writel_relaxed(bank->context.debounce, bank->base + in omap_clear_gpio_debounce()
[all …]
/drivers/media/rc/
Dir-hix5hd2.c20 #ifndef writel_relaxed
21 # define writel_relaxed writel macro
102 writel_relaxed(0x01, priv->base + IR_ENABLE); in hix5hd2_ir_config()
120 writel_relaxed(val, priv->base + IR_CONFIG); in hix5hd2_ir_config()
122 writel_relaxed(0x00, priv->base + IR_INTM); in hix5hd2_ir_config()
124 writel_relaxed(0x01, priv->base + IR_START); in hix5hd2_ir_config()
162 writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC); in hix5hd2_ir_rx_interrupt()
191 writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC); in hix5hd2_ir_rx_interrupt()
193 writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC); in hix5hd2_ir_rx_interrupt()
318 writel_relaxed(0x01, priv->base + IR_ENABLE); in hix5hd2_ir_resume()
[all …]
/drivers/mfd/
Dmcp-sa11x0.c56 writel_relaxed(m->mccr0, MCCR0(m)); in mcp_sa11x0_set_telecom_divisor()
68 writel_relaxed(m->mccr0, MCCR0(m)); in mcp_sa11x0_set_audio_divisor()
84 writel_relaxed(reg << 17 | MCDR2_Wr | (val & 0xffff), MCDR2(m)); in mcp_sa11x0_write()
111 writel_relaxed(reg << 17 | MCDR2_Rd, MCDR2(m)); in mcp_sa11x0_read()
133 writel_relaxed(m->mccr0, MCCR0(m)); in mcp_sa11x0_enable()
141 writel_relaxed(m->mccr0, MCCR0(m)); in mcp_sa11x0_disable()
211 writel_relaxed(-1, MCSR(m)); in mcp_sa11x0_probe()
212 writel_relaxed(m->mccr1, MCCR1(m)); in mcp_sa11x0_probe()
213 writel_relaxed(m->mccr0, MCCR0(m)); in mcp_sa11x0_probe()
279 writel_relaxed(m->mccr1, MCCR1(m)); in mcp_sa11x0_resume()
[all …]
/drivers/watchdog/
Dsa1100_wdt.c57 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); in sa1100dog_open()
58 writel_relaxed(OSSR_M3, OSSR); in sa1100dog_open()
59 writel_relaxed(OWER_WME, OWER); in sa1100dog_open()
60 writel_relaxed(readl_relaxed(OIER) | OIER_E3, OIER); in sa1100dog_open()
83 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); in sa1100dog_write()
117 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); in sa1100dog_ioctl()
132 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); in sa1100dog_ioctl()
/drivers/hsi/controllers/
Domap_ssi_port.c267 writel_relaxed(d_addr, gdd + SSI_GDD_CDSA_REG(lch)); in ssi_start_dma()
268 writel_relaxed(s_addr, gdd + SSI_GDD_CSSA_REG(lch)); in ssi_start_dma()
275 writel_relaxed(tmp, omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG); in ssi_start_dma()
463 writel_relaxed(SSI_MODE_SLEEP, sst + SSI_SST_MODE_REG); in ssi_setup()
464 writel_relaxed(SSI_MODE_SLEEP, ssr + SSI_SSR_MODE_REG); in ssi_setup()
468 writel_relaxed(31, sst + SSI_SST_FRAMESIZE_REG); in ssi_setup()
469 writel_relaxed(div, sst + SSI_SST_DIVISOR_REG); in ssi_setup()
470 writel_relaxed(cl->tx_cfg.num_hw_channels, sst + SSI_SST_CHANNELS_REG); in ssi_setup()
471 writel_relaxed(cl->tx_cfg.arb_mode, sst + SSI_SST_ARBMODE_REG); in ssi_setup()
472 writel_relaxed(cl->tx_cfg.mode, sst + SSI_SST_MODE_REG); in ssi_setup()
[all …]

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