| /arch/arm/boot/compressed/ |
| D | head-sharpsl.S | 35 mrc p15, 0, r4, c0, c0 @ Get Processor ID
53 ldr r6, [r1, #0] @ Load Chip ID
96 .word 0x69052d00 @ PXA255 Processor ID
98 .word 0x69054100 @ PXA270 Processor ID
100 .word 0x57411002 @ w100 Chip ID
102 .word 0x08010000 @ w100 Chip ID Reg Address
146 ldrb r2, [r1, #20] @ NAND Manufacturer ID
147 ldrb r3, [r1, #20] @ NAND Chip ID
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| D | head-vt8500.S | 16 @ Compare the SCC ID register against a list of known values
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| D | head.S | 136 1: mov r7, r1 @ save architecture ID
730 mrc p15, 0, r9, c0, c0 @ get processor ID
773 .word 0x00000000 @ old ARM ID
824 @ Everything from here on will be the new ID system.
871 @ These match on the architecture ID
1116 teq r3, r9 @ cache ID register present?
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| /arch/arm/mm/ |
| D | cache-v4.S | 42 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
61 mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache
116 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
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| D | cache-v3.S | 54 mcreq p15, 0, ip, c7, c0, 0 @ flush ID cache
105 mcr p15, 0, r0, c7, c0, 0 @ flush ID cache
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| D | proc-v7.S | 99 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
101 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
115 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
118 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
120 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
178 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
372 .long 0x000f0000 @ Required ID value
373 .long 0x000f0000 @ Mask for ID
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| D | proc-v6.S | 110 mcr p15, 0, r1, c13, c0, 1 @ set context ID
139 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
154 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
157 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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| D | proc-sa1100.S | 178 mrc p15, 0, r4, c3, c0, 0 @ domain ID
193 mcr p15, 0, r4, c3, c0, 0 @ domain ID
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| D | proc-v7-2level.S | 52 mcr p15, 0, r1, c13, c0, 1 @ set context ID
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| D | proc-arm920.S | 390 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
402 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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| D | proc-arm926.S | 405 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
417 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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| D | proc-xsc3.S | 419 mrc p15, 0, r7, c3, c0, 0 @ domain ID
437 mcr p15, 0, r7, c3, c0, 0 @ domain ID
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| /arch/mips/include/asm/pmc-sierra/msp71xx/ |
| D | msp_pci.h | 29 #define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220)) argument
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| /arch/arm/mach-omap2/ |
| D | omap-smc.S | 46 mov r1, #0x0 @ Process ID
48 mov r12, #0x00 @ Secure Service ID
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| D | sleep34xx.S | 106 mov r0, #25 @ set service ID for PPA
107 mov r12, r0 @ copy secure service ID in r12
471 mov r0, #40 @ set service ID for PPA
472 mov r12, r0 @ copy secure Service ID in r12
481 mov r0, #42 @ set service ID for PPA
482 mov r12, r0 @ copy secure Service ID in r12
494 @ set service ID for PPA
496 mov r12, r0 @ copy service ID in r12
497 mov r1, #0 @ set task ID for ROM code in r1
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| D | sleep44xx.S | 263 mov r1, #0x0 @ Process ID
266 mov r12, #0x00 @ Secure Service ID
301 mov r1, #0x0 @ Process ID
304 mov r12, #0x00 @ Secure Service ID
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| D | omap_phy_internal.c | 110 int omap4430_phy_power(struct device *dev, int ID, int on) in omap4430_phy_power() argument
113 if (ID) in omap4430_phy_power()
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| /arch/arm/ |
| D | Kconfig-nommu | 29 hex 'Hard wire the processor ID'
33 If processor has no CP15 register, this processor ID is
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| /arch/x86/include/asm/ |
| D | io_apic.h | 43 ID : 8; member
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| /arch/x86/kernel/ |
| D | head_32.S | 392 xorl $0x240000,%eax # flip AC and ID bits in EFLAGS
404 testl $0x200000,%eax # check if ID bit changed
408 xorl %eax,%eax # call CPUID with 0 -> return vendor ID
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| /arch/x86/kernel/apic/ |
| D | io_apic.c | 1642 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); in print_IO_APIC()
2118 reg_00.bits.ID); in setup_ioapic_ids_from_mpc_nocheck()
2119 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; in setup_ioapic_ids_from_mpc_nocheck()
2164 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) in setup_ioapic_ids_from_mpc_nocheck()
2171 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); in setup_ioapic_ids_from_mpc_nocheck()
2182 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) in setup_ioapic_ids_from_mpc_nocheck()
3082 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { in resume_ioapic_id()
3083 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); in resume_ioapic_id()
3748 "%d\n", ioapic, apic_id, reg_00.bits.ID); in io_apic_get_unique_id()
3749 apic_id = reg_00.bits.ID; in io_apic_get_unique_id()
[all …]
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| /arch/arm/kernel/ |
| D | head-common.S | 98 str r9, [r4] @ Save processor ID
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| /arch/mips/include/asm/mach-cavium-octeon/ |
| D | kernel-entry-init.h | 46 # Read the processor ID register
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| /arch/arm/plat-omap/ |
| D | Kconfig | 166 int "Service ID for the support routine to set L2 AUX control"
170 PPA routine service ID for setting L2 auxiliary control register.
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| /arch/arm/plat-omap/include/plat/ |
| D | usb.h | 104 extern int omap4430_phy_power(struct device *dev, int ID, int on);
|