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Searched refs:chan (Results 1 – 25 of 77) sorted by relevance

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/arch/arm/plat-s3c24xx/
Ddma.c53 #define dma_regaddr(chan, reg) ((chan)->regs + (reg)) argument
56 #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg)) argument
59 dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val) in dma_wrreg() argument
62 writel(val, dma_regaddr(chan, reg)); in dma_wrreg()
66 #define dma_rdreg(chan, reg) readl((chan)->regs + (reg)) argument
86 dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs) in dmadbg_capture() argument
88 regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC); in dmadbg_capture()
89 regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC); in dmadbg_capture()
90 regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT); in dmadbg_capture()
91 regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON); in dmadbg_capture()
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/arch/um/drivers/
Dchan_kern.c102 static int open_one_chan(struct chan *chan) in open_one_chan() argument
106 if (chan->opened) in open_one_chan()
109 if (chan->ops->open == NULL) in open_one_chan()
111 else fd = (*chan->ops->open)(chan->input, chan->output, chan->primary, in open_one_chan()
112 chan->data, &chan->dev); in open_one_chan()
118 (*chan->ops->close)(fd, chan->data); in open_one_chan()
122 chan->fd = fd; in open_one_chan()
124 chan->opened = 1; in open_one_chan()
131 struct chan *chan; in open_chan() local
135 chan = list_entry(ele, struct chan, list); in open_chan()
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Dchan.h15 struct chan { struct
34 extern int write_chan(struct chan *chan, const char *buf, int len, argument
36 extern int console_write_chan(struct chan *chan, const char *buf,
39 extern void deactivate_chan(struct chan *chan, int irq);
40 extern void reactivate_chan(struct chan *chan, int irq);
41 extern void chan_enable_winch(struct chan *chan, struct tty_struct *tty);
/arch/sh/drivers/dma/
Ddma-sh.c32 static inline unsigned int get_dmte_irq(unsigned int chan) in get_dmte_irq() argument
35 if (chan < ARRAY_SIZE(dmte_irq_map)) in get_dmte_irq()
36 irq = dmte_irq_map[chan]; in get_dmte_irq()
56 static inline unsigned int calc_xmit_shift(struct dma_channel *chan) in calc_xmit_shift() argument
58 u32 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR); in calc_xmit_shift()
73 struct dma_channel *chan = dev_id; in dma_tei() local
76 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR); in dma_tei()
82 __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR)); in dma_tei()
84 wake_up(&chan->wait_queue); in dma_tei()
89 static int sh_dmac_request_dma(struct dma_channel *chan) in sh_dmac_request_dma() argument
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Ddma-g2.c64 struct dma_channel *chan = info->channels + i; in g2_dma_interrupt() local
66 wake_up(&chan->wait_queue); in g2_dma_interrupt()
76 static int g2_enable_dma(struct dma_channel *chan) in g2_enable_dma() argument
78 unsigned int chan_nr = chan->chan; in g2_enable_dma()
86 static int g2_disable_dma(struct dma_channel *chan) in g2_disable_dma() argument
88 unsigned int chan_nr = chan->chan; in g2_disable_dma()
96 static int g2_xfer_dma(struct dma_channel *chan) in g2_xfer_dma() argument
98 unsigned int chan_nr = chan->chan; in g2_xfer_dma()
100 if (chan->sar & 31) { in g2_xfer_dma()
101 printk("g2dma: unaligned source 0x%lx\n", chan->sar); in g2_xfer_dma()
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Ddma-api.c26 struct dma_info *get_dma_info(unsigned int chan) in get_dma_info() argument
35 if ((chan < info->first_vchannel_nr) || in get_dma_info()
36 (chan >= info->first_vchannel_nr + info->nr_channels)) in get_dma_info()
75 struct dma_channel *get_dma_channel(unsigned int chan) in get_dma_channel() argument
77 struct dma_info *info = get_dma_info(chan); in get_dma_channel()
86 if (channel->vchan == chan) in get_dma_channel()
94 int get_dma_residue(unsigned int chan) in get_dma_residue() argument
96 struct dma_info *info = get_dma_info(chan); in get_dma_residue()
97 struct dma_channel *channel = get_dma_channel(chan); in get_dma_residue()
157 if (request_dma(channel->chan, dev_id) == 0) in request_dma_bycap()
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Ddma-pvr2.c41 static int pvr2_request_dma(struct dma_channel *chan) in pvr2_request_dma() argument
51 static int pvr2_get_dma_residue(struct dma_channel *chan) in pvr2_get_dma_residue() argument
56 static int pvr2_xfer_dma(struct dma_channel *chan) in pvr2_xfer_dma() argument
58 if (chan->sar || !chan->dar) in pvr2_xfer_dma()
63 __raw_writel(chan->dar, PVR2_DMA_ADDR); in pvr2_xfer_dma()
64 __raw_writel(chan->count, PVR2_DMA_COUNT); in pvr2_xfer_dma()
65 __raw_writel(chan->mode & DMA_MODE_MASK, PVR2_DMA_MODE); in pvr2_xfer_dma()
/arch/mips/include/asm/mach-au1x00/
Dau1000_dma.h156 struct dma_chan *chan = get_dma_chan(dmanr); in enable_dma_buffer0() local
158 if (!chan) in enable_dma_buffer0()
160 au_writel(DMA_BE0, chan->io + DMA_MODE_SET); in enable_dma_buffer0()
165 struct dma_chan *chan = get_dma_chan(dmanr); in enable_dma_buffer1() local
167 if (!chan) in enable_dma_buffer1()
169 au_writel(DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffer1()
173 struct dma_chan *chan = get_dma_chan(dmanr); in enable_dma_buffers() local
175 if (!chan) in enable_dma_buffers()
177 au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffers()
182 struct dma_chan *chan = get_dma_chan(dmanr); in start_dma() local
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/arch/arm/mach-s3c64xx/
Ddma.c52 static void dbg_showchan(struct s3c2410_dma_chan *chan) in dbg_showchan() argument
55 chan->number, in dbg_showchan()
56 readl(chan->regs + PL080_CH_SRC_ADDR), in dbg_showchan()
57 readl(chan->regs + PL080_CH_DST_ADDR), in dbg_showchan()
58 readl(chan->regs + PL080_CH_LLI), in dbg_showchan()
59 readl(chan->regs + PL080_CH_CONTROL), in dbg_showchan()
60 readl(chan->regs + PL080S_CH_CONTROL2), in dbg_showchan()
61 readl(chan->regs + PL080S_CH_CONFIG)); in dbg_showchan()
71 static void dbg_showbuffs(struct s3c2410_dma_chan *chan) in dbg_showbuffs() argument
77 chan->number, chan->next, chan->curr, chan->end); in dbg_showbuffs()
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/arch/arm/kernel/
Ddma.c31 static inline dma_t *dma_channel(unsigned int chan) in dma_channel() argument
33 if (chan >= MAX_DMA_CHANNELS) in dma_channel()
36 return dma_chan[chan]; in dma_channel()
39 int __init isa_dma_add(unsigned int chan, dma_t *dma) in isa_dma_add() argument
46 if (dma_chan[chan]) in isa_dma_add()
48 dma_chan[chan] = dma; in isa_dma_add()
57 int request_dma(unsigned int chan, const char *device_id) in request_dma() argument
59 dma_t *dma = dma_channel(chan); in request_dma()
74 ret = dma->d_ops->request(chan, dma); in request_dma()
82 printk(KERN_ERR "dma: trying to allocate DMA%d\n", chan); in request_dma()
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Ddma-isa.c47 static int isa_get_dma_residue(unsigned int chan, dma_t *dma) in isa_get_dma_residue() argument
49 unsigned int io_port = isa_dma_port[chan][ISA_DMA_COUNT]; in isa_get_dma_residue()
55 return chan < 4 ? count : (count << 1); in isa_get_dma_residue()
58 static void isa_enable_dma(unsigned int chan, dma_t *dma) in isa_enable_dma() argument
65 mode = (chan & 3) | dma->dma_mode; in isa_enable_dma()
100 outb(address >> 16, isa_dma_port[chan][ISA_DMA_PGLO]); in isa_enable_dma()
101 outb(address >> 24, isa_dma_port[chan][ISA_DMA_PGHI]); in isa_enable_dma()
103 if (chan >= 4) { in isa_enable_dma()
108 outb(0, isa_dma_port[chan][ISA_DMA_CLRFF]); in isa_enable_dma()
110 outb(address, isa_dma_port[chan][ISA_DMA_ADDR]); in isa_enable_dma()
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/arch/sh/drivers/pci/
Dpci-sh7751.c22 static int __init __area_sdram_check(struct pci_channel *chan, in __area_sdram_check() argument
34 pci_write_reg(chan, word, SH4_PCIBCR1); in __area_sdram_check()
43 pci_write_reg(chan, word, SH4_PCIBCR2); in __area_sdram_check()
80 struct pci_channel *chan = &sh7751_pci_controller; in sh7751_pci_init() local
86 chan->reg_base = 0xfe200000; in sh7751_pci_init()
89 id = pci_read_reg(chan, SH7751_PCICONF0); in sh7751_pci_init()
102 pci_write_reg(chan, 0, SH4_PCICLKR); in sh7751_pci_init()
105 pci_write_reg(chan, word, SH4_PCIPINT); in sh7751_pci_init()
113 pci_write_reg(chan, word, SH7751_PCICONF1); in sh7751_pci_init()
117 pci_write_reg(chan, word, SH7751_PCICONF2); in sh7751_pci_init()
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Dpcie-sh7786.c152 static int __init phy_wait_for_ack(struct pci_channel *chan) in phy_wait_for_ack() argument
157 if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK)) in phy_wait_for_ack()
166 static int __init pci_wait_for_irq(struct pci_channel *chan, unsigned int mask) in pci_wait_for_irq() argument
171 if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask) in pci_wait_for_irq()
180 static void __init phy_write_reg(struct pci_channel *chan, unsigned int addr, in phy_write_reg() argument
189 pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR); in phy_write_reg()
190 pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR); in phy_write_reg()
192 phy_wait_for_ack(chan); in phy_write_reg()
195 pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR); in phy_write_reg()
196 pci_write_reg(chan, 0, SH4A_PCIEPHYADRR); in phy_write_reg()
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Dfixups-rts7751r2d.c42 int pci_fixup_pcic(struct pci_channel *chan) in pci_fixup_pcic() argument
48 pci_write_reg(chan, bcr1, SH4_PCIBCR1); in pci_fixup_pcic()
51 pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM); in pci_fixup_pcic()
52 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM); in pci_fixup_pcic()
54 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1); in pci_fixup_pcic()
55 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4); in pci_fixup_pcic()
59 pci_write_reg(chan, mcr, SH4_PCIMCR); in pci_fixup_pcic()
61 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5); in pci_fixup_pcic()
62 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6); in pci_fixup_pcic()
63 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0); in pci_fixup_pcic()
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Dpci-sh7780.c249 struct pci_channel *chan = &sh7780_pci_controller; in sh7780_pci_init() local
258 chan->reg_base = 0xfe040000; in sh7780_pci_init()
265 chan->reg_base + SH4_PCICR); in sh7780_pci_init()
274 id = __raw_readw(chan->reg_base + PCI_VENDOR_ID); in sh7780_pci_init()
280 id = __raw_readw(chan->reg_base + PCI_DEVICE_ID); in sh7780_pci_init()
294 __raw_readb(chan->reg_base + PCI_REVISION_ID)); in sh7780_pci_init()
301 chan->reg_base + SH4_PCICR); in sh7780_pci_init()
311 __raw_writel(memphys + SZ_512M, chan->reg_base + SH4_PCILAR1); in sh7780_pci_init()
313 chan->reg_base + SH4_PCILSR1); in sh7780_pci_init()
319 __raw_writel(0, chan->reg_base + SH4_PCILAR1); in sh7780_pci_init()
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Dfixups-landisk.c40 int pci_fixup_pcic(struct pci_channel *chan) in pci_fixup_pcic() argument
46 pci_write_reg(chan, bcr1, SH4_PCIBCR1); in pci_fixup_pcic()
50 pci_write_reg(chan, mcr, SH4_PCIMCR); in pci_fixup_pcic()
52 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5); in pci_fixup_pcic()
53 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6); in pci_fixup_pcic()
54 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0); in pci_fixup_pcic()
55 pci_write_reg(chan, 0x00000000, SH4_PCILAR1); in pci_fixup_pcic()
/arch/arm/include/asm/
Ddma.h53 #define clear_dma_ff(chan) argument
60 extern void set_dma_page(unsigned int chan, char pagenr);
66 extern int request_dma(unsigned int chan, const char * device_id);
72 extern void free_dma(unsigned int chan);
79 extern void enable_dma(unsigned int chan);
86 extern void disable_dma(unsigned int chan);
90 extern int dma_channel_active(unsigned int chan);
98 extern void set_dma_sg(unsigned int chan, struct scatterlist *sg, int nr_sg);
106 extern void __set_dma_addr(unsigned int chan, void *addr);
107 #define set_dma_addr(chan, addr) \ argument
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/arch/sh/include/asm/
Ddma.h66 int (*request)(struct dma_channel *chan);
67 void (*free)(struct dma_channel *chan);
69 int (*get_residue)(struct dma_channel *chan);
70 int (*xfer)(struct dma_channel *chan);
71 int (*configure)(struct dma_channel *chan, unsigned long flags);
72 int (*extend)(struct dma_channel *chan, unsigned long op, void *param);
78 unsigned int chan; /* DMAC channel number */ member
121 extern int dma_xfer(unsigned int chan, unsigned long from,
124 #define dma_write(chan, from, to, size) \ argument
125 dma_xfer(chan, from, to, size, DMA_MODE_WRITE)
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/arch/mips/alchemy/common/
Ddma.c104 struct dma_chan *chan; in au1000_dma_read_proc() local
107 chan = get_dma_chan(i); in au1000_dma_read_proc()
108 if (chan != NULL) in au1000_dma_read_proc()
110 i, chan->dev_str); in au1000_dma_read_proc()
136 struct dma_chan *chan; in dump_au1000_dma_channel() local
140 chan = &au1000_dma_table[dmanr]; in dump_au1000_dma_channel()
144 au_readl(chan->io + DMA_MODE_SET)); in dump_au1000_dma_channel()
146 au_readl(chan->io + DMA_PERIPHERAL_ADDR)); in dump_au1000_dma_channel()
148 au_readl(chan->io + DMA_BUFFER0_START)); in dump_au1000_dma_channel()
150 au_readl(chan->io + DMA_BUFFER1_START)); in dump_au1000_dma_channel()
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/arch/arm/mach-iop13xx/include/mach/
Dadma.h25 #define ADMA_ACCR(chan) (chan->mmr_base + 0x0) argument
26 #define ADMA_ACSR(chan) (chan->mmr_base + 0x4) argument
27 #define ADMA_ADAR(chan) (chan->mmr_base + 0x8) argument
28 #define ADMA_IIPCR(chan) (chan->mmr_base + 0x18) argument
29 #define ADMA_IIPAR(chan) (chan->mmr_base + 0x1c) argument
30 #define ADMA_IIPUAR(chan) (chan->mmr_base + 0x20) argument
31 #define ADMA_ANDAR(chan) (chan->mmr_base + 0x24) argument
32 #define ADMA_ADCR(chan) (chan->mmr_base + 0x28) argument
33 #define ADMA_CARMD(chan) (chan->mmr_base + 0x2c) argument
34 #define ADMA_ABCR(chan) (chan->mmr_base + 0x30) argument
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/arch/arm/plat-samsung/
Ddma.c46 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); in s3c2410_dma_set_opfn() local
48 if (chan == NULL) in s3c2410_dma_set_opfn()
51 pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn); in s3c2410_dma_set_opfn()
53 chan->op_fn = rtn; in s3c2410_dma_set_opfn()
61 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); in s3c2410_dma_set_buffdone_fn() local
63 if (chan == NULL) in s3c2410_dma_set_buffdone_fn()
66 pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn); in s3c2410_dma_set_buffdone_fn()
68 chan->callback_fn = rtn; in s3c2410_dma_set_buffdone_fn()
76 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); in s3c2410_dma_setflags() local
78 if (chan == NULL) in s3c2410_dma_setflags()
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/arch/arm/include/asm/hardware/
Diop3xx-adma.h26 #define DMA_CCR(chan) (chan->mmr_base + 0x0) argument
27 #define DMA_CSR(chan) (chan->mmr_base + 0x4) argument
28 #define DMA_DAR(chan) (chan->mmr_base + 0xc) argument
29 #define DMA_NDAR(chan) (chan->mmr_base + 0x10) argument
30 #define DMA_PADR(chan) (chan->mmr_base + 0x14) argument
31 #define DMA_PUADR(chan) (chan->mmr_base + 0x18) argument
32 #define DMA_LADR(chan) (chan->mmr_base + 0x1c) argument
33 #define DMA_BCR(chan) (chan->mmr_base + 0x20) argument
34 #define DMA_DCR(chan) (chan->mmr_base + 0x24) argument
37 #define AAU_ACR(chan) (chan->mmr_base + 0x0) argument
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/arch/xtensa/variants/s6000/include/variant/
Ddmac.h145 static inline int s6dmac_fifo_full(u32 dmac, int chan) in s6dmac_fifo_full() argument
147 return (readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL) in s6dmac_fifo_full()
151 static inline int s6dmac_termcnt_irq(u32 dmac, int chan) in s6dmac_termcnt_irq() argument
153 u32 m = 1 << chan; in s6dmac_termcnt_irq()
160 static inline int s6dmac_pendcnt_irq(u32 dmac, int chan) in s6dmac_pendcnt_irq() argument
162 u32 m = 1 << chan; in s6dmac_pendcnt_irq()
169 static inline int s6dmac_lowwmark_irq(u32 dmac, int chan) in s6dmac_lowwmark_irq() argument
171 int r = (readl(dmac + S6_DMA_LOWWMRKIRQSTAT) & (1 << chan)) ? 1 : 0; in s6dmac_lowwmark_irq()
173 writel(1 << chan, dmac + S6_DMA_LOWWMRKIRQCLR); in s6dmac_lowwmark_irq()
177 static inline u32 s6dmac_pending_count(u32 dmac, int chan) in s6dmac_pending_count() argument
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/arch/powerpc/platforms/pasemi/
Ddma_lib.c142 static void pasemi_free_tx_chan(int chan) in pasemi_free_tx_chan() argument
144 BUG_ON(test_bit(chan, txch_free)); in pasemi_free_tx_chan()
145 set_bit(chan, txch_free); in pasemi_free_tx_chan()
161 static void pasemi_free_rx_chan(int chan) in pasemi_free_rx_chan() argument
163 BUG_ON(test_bit(chan, rxch_free)); in pasemi_free_rx_chan()
164 set_bit(chan, rxch_free); in pasemi_free_rx_chan()
186 struct pasemi_dmachan *chan; in pasemi_dma_alloc_chan() local
195 chan = buf + offset; in pasemi_dma_alloc_chan()
197 chan->priv = buf; in pasemi_dma_alloc_chan()
202 chan->chno = chno; in pasemi_dma_alloc_chan()
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/arch/arm/mach-bcmring/csp/dmac/
DdmacHw_extra.c74 int chan; in DisplayRegisterContents() local
144 for (chan = 0; chan < 8; chan++) { in DisplayRegisterContents()
149 module, chan, in DisplayRegisterContents()
150 (uint32_t) (dmacHw_REG_SAR(module, chan))); in DisplayRegisterContents()
153 module, chan, in DisplayRegisterContents()
154 (uint32_t) (dmacHw_REG_DAR(module, chan))); in DisplayRegisterContents()
157 module, chan, in DisplayRegisterContents()
158 (uint32_t) (dmacHw_REG_LLP(module, chan))); in DisplayRegisterContents()
161 module, chan, in DisplayRegisterContents()
162 (uint32_t) (dmacHw_REG_CTL_LO(module, chan))); in DisplayRegisterContents()
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