Searched refs:readl_relaxed (Results 1 – 25 of 41) sorted by relevance
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58 while (readl_relaxed(reg) & mask) in cache_wait_way()360 l2x0_cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); in l2x0_init()361 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); in l2x0_init()406 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) { in l2x0_init()505 u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) & in pl310_save()508 l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base + in pl310_save()510 l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base + in pl310_save()512 l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base + in pl310_save()514 l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base + in pl310_save()521 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base + in pl310_save()[all …]
63 WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0))); in sirfsoc_timer_interrupt()80 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI); in sirfsoc_timer_read()81 cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); in sirfsoc_timer_read()92 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); in sirfsoc_timer_set_next_event()96 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); in sirfsoc_timer_set_next_event()104 u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); in sirfsoc_timer_set_mode()128 sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); in sirfsoc_clocksource_suspend()
91 sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0); in sirfsoc_irq_suspend()92 sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1); in sirfsoc_irq_suspend()93 sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); in sirfsoc_irq_suspend()94 sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); in sirfsoc_irq_suspend()
36 while (readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL)) in sirfsoc_rtc_iobrg_wait_sync()62 return readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA); in __sirfsoc_rtc_iobrg_readl()
34 val = readl_relaxed(src_base + SRC_SCR); in imx_enable_cpu()51 val = readl_relaxed(src_base + SRC_SCR); in imx_src_prepare_restart()72 val = readl_relaxed(src_base + SRC_SCR); in imx_src_init()
37 val = readl_relaxed(reg); in imx_mmdc_probe()42 while (!(readl_relaxed(reg) & 1 << BP_MMDC_MAPSR_PSS) && --timeout) in imx_mmdc_probe()
38 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); in imx_gpc_pre_suspend()81 val = readl_relaxed(reg); in imx_gpc_irq_unmask()96 val = readl_relaxed(reg); in imx_gpc_irq_mask()
467 val = readl_relaxed(reg); in pll_enable()476 while (!(readl_relaxed(reg) & BM_PLL_LOCK) && --timeout) in pll_enable()483 val = readl_relaxed(reg); in pll_enable()496 val = readl_relaxed(reg); in pll_disable()507 u32 div = (readl_relaxed(PLL1_SYS) & BM_PLL_SYS_DIV_SELECT) >> in pll1_sys_get_rate()521 val = readl_relaxed(PLL1_SYS); in pll1_sys_set_rate()531 u32 div = (readl_relaxed(PLL8_ENET) & BM_PLL_ENET_DIV_SELECT) >> in pll8_enet_get_rate()569 val = readl_relaxed(PLL8_ENET); in pll8_enet_set_rate()581 u32 mfn = readl_relaxed(reg + PLL_NUM_OFFSET); in pll_av_get_rate()582 u32 mfd = readl_relaxed(reg + PLL_DENOM_OFFSET); in pll_av_get_rate()[all …]
199 val = readl_relaxed(base + GIC_DIST_CONFIG + confoff); in gic_set_type()209 if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { in gic_set_type()248 val = readl_relaxed(reg) & ~mask; in gic_set_affinity()278 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); in gic_handle_irq()307 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); in gic_handle_cascade_irq()435 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); in gic_dist_save()439 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); in gic_dist_save()443 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); in gic_dist_save()507 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); in gic_cpu_save()511 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); in gic_cpu_save()[all …]
75 return ~readl_relaxed(sched_clock_base + TIMER_VALUE); in sp804_read()
53 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_interrupt()64 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_set_next_event()77 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_set_mode()111 return readl_relaxed(source_base + TIMER_COUNT_VAL); in msm_read_timer_count()
27 while (readl_relaxed(base + UART01x_FR) & UART01x_FR_TXFF) in putc()
225 irqnr = readl_relaxed(base_addr + 0x98); in omap_intc_handle_irq()229 irqnr = readl_relaxed(base_addr + 0xb8); in omap_intc_handle_irq()233 irqnr = readl_relaxed(base_addr + 0xd8); in omap_intc_handle_irq()237 irqnr = readl_relaxed(base_addr + 0xf8); in omap_intc_handle_irq()244 irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET); in omap_intc_handle_irq()
54 writel_relaxed(readl_relaxed(dram_sync), dram_sync); in omap_bus_sync()55 writel_relaxed(readl_relaxed(sram_sync), sram_sync); in omap_bus_sync()
51 readl_relaxed(addr); in flowctrl_update()
72 reg = readl_relaxed(reset); in tegra_assert_system_reset()
112 id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804); in tegra_init_fuse()
121 num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) & 0x1f; in tegra_init_irq()
146 while (readl_relaxed(MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR) in mxs_clkctrl_timeout()
76 u &= readl_relaxed(PMU_INTERRUPT_CAUSE); in pmu_irq_ack()
59 #define readl_relaxed(addr) readl(addr) macro
152 # define platform_readl_relaxed ia64_mv.readl_relaxed196 ia64_mv_readl_relaxed_t *readl_relaxed; member
382 #define readl_relaxed(a) __readl_relaxed((a)) macro390 #define __raw_readl_relaxed readl_relaxed
156 #define readl_relaxed readl macro
88 #define readl_relaxed(addr) readl(addr) macro