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/arch/mips/kernel/
Dr4k_switch.S49 mfc0 t1, CP0_STATUS
50 LONG_S t1, THREAD_STATUS(a0)
59 li t1, _TIF_USEDFPU
60 and t2, t0, t1
62 nor t1, zero, t1
64 and t0, t0, t1
71 li t1, ~ST0_CU1
72 and t0, t0, t1
75 fpu_save_double a0 t0 t1 # c0_status passed in t0
76 # clobbers t1
[all …]
Docteon_switch.S39 mfc0 t1, CP0_STATUS
40 LONG_S t1, THREAD_STATUS(a0)
50 li t1, ST0_CU2
51 xor t0, t1
56 or t0, t1
66 li t1, ST0_CU2
67 xor t0, t1
81 li t1, -32768 /* Base address of CVMSEG */
86 LONG_L t8, 0(t1) /* Load from CVMSEG */
88 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
[all …]
Dr2300_switch.S50 mfc0 t1, CP0_STATUS
51 sw t1, THREAD_STATUS(a0)
60 li t1, _TIF_USEDFPU
61 and t2, t0, t1
63 nor t1, zero, t1
65 and t0, t0, t1
72 li t1, ~ST0_CU1
73 and t0, t0, t1
86 addiu t1, $28, _THREAD_SIZE - 32
87 sw t1, kernelsp
[all …]
Dsmtc-asm.S117 ori t1,t0,TCSTATUS_IXMT
118 mtc0 t1,CP0_TCSTATUS
121 subu t1,sp,PT_SIZE
122 sw ra,PT_EPC(t1)
123 sw a0,PT_PADSLOT4(t1)
125 sw t2,PT_PADSLOT5(t1)
127 sw t0,PT_TCSTATUS(t1)
Dhead.S44 dsll t1, NASID_SHFT # Shift text nasid into place
46 or t1, t1, t0 # Physical load address of kernel text
48 dsrl t1, 12 # 4K pfn
50 dsll t1, 6 # Get pfn into place
53 or t0, t0, t1
86 li t1, ST0_CU0 | 0x08001c00
87 or t0, t1
178 PTR_LA t1, __bss_stop - LONGSIZE
182 bne t0, t1, 1b
195 set_saved_sp sp, t0, t1
/arch/mips/netlogic/common/
Dsmpboot.S59 mfcr t1, t0
62 or t1, t1, t2
64 and t1, t1, t2
65 mtcr t1, t0
68 lui t1, 0x0100 /* Experimental: Disable BRU accepting ALU ops */
69 mtcr t1, t0
104 mfc0 t1, CP0_EBASE, 1
105 srl t1, 5
106 andi t1, 0x3 /* t1 <- node */
108 mul t3, t2, t1 /* t3 = node * 0x40000 */
[all …]
/arch/mips/include/asm/sibyte/
Dboard.h42 #define setleds(t0, t1, c0, c1, c2, c3) \
44 li t1, c0; \
45 sb t1, 0x18(t0); \
46 li t1, c1; \
47 sb t1, 0x10(t0); \
48 li t1, c2; \
49 sb t1, 0x08(t0); \
50 li t1, c3; \
51 sb t1, 0x00(t0)
53 #define setleds(t0, t1, c0, c1, c2, c3)
/arch/alpha/lib/
Dstxcpy.S48 mskqh t1, a1, t3 # e0 :
49 ornot t1, t2, t2 # .. e1 :
52 or t0, t3, t1 # e0 :
60 stq_u t1, 0(a0) # e0 :
62 ldq_u t1, 0(a1) # e0 :
64 cmpbge zero, t1, t8 # e0 (stall)
84 zapnot t1, t6, t1 # e0 : clear src bytes >= null
87 or t0, t1, t1 # e1 :
89 1: stq_u t1, 0(a0) # e0 :
108 ldq_u t1, 0(a1) # e0 : load first src word
[all …]
Dev6-stxcpy.S59 mskqh t1, a1, t3 # U :
60 ornot t1, t2, t2 # E : (stall)
64 or t0, t3, t1 # E : (stall)
73 stq_u t1, 0(a0) # L :
78 ldq_u t1, 0(a1) # L : Latency=3
80 cmpbge zero, t1, t8 # E : (3 cycle stall)
99 zapnot t1, t6, t1 # U : clear src bytes >= null (stall)
103 or t0, t1, t1 # E : (stall)
107 1: stq_u t1, 0(a0) # L :
128 ldq_u t1, 0(a1) # L : load first src word
[all …]
Dstrlen_user.S48 lda t1, -1(zero)
49 insqh t1, a0, t1
51 or t1, t0, t0
53 cmpbge zero, t0, t1 # t1 <- bitmask: bit i == 1 <==> i-th byte == 0
56 bne t1, $found
66 cmpbge zero, t0, t1
67 beq t1, $loop
69 $found: negq t1, t2 # clear all but least set bit
70 and t1, t2, t1
72 and t1, 0xf0, t2 # binary search for that set bit
[all …]
Dstrncpy_from_user.S45 mskqh t1, a1, t3 # e0 :
46 ornot t1, t2, t2 # .. e1 :
84 ldq_u t1, 0(a0) # e0 :
89 zap t1, t8, t1 # .. e1 : clear dst bytes <= null
90 or t0, t1, t0 # e1 :
107 xor a0, a1, t1 # e0 :
109 and t1, 7, t1 # e0 :
116 bne t1, $unaligned # .. e1 :
120 EX( ldq_u t1, 0(a1) ) # e0 : load first src word
147 or t1, t4, t1 # e1 : first aligned src word complete
[all …]
Dstxncpy.S56 mskqh t1, a1, t3 # e0 :
57 ornot t1, t2, t2 # .. e1 :
95 ldq_u t1, 0(a0) # e0 :
100 zap t1, t8, t1 # .. e1 : clear dst bytes <= null
101 or t0, t1, t0 # e1 :
121 xor a0, a1, t1 # e0 :
123 and t1, 7, t1 # e0 :
130 bne t1, $unaligned # .. e1 :
134 ldq_u t1, 0(a1) # e0 : load first src word
161 or t1, t4, t1 # e1 : first aligned src word complete
[all …]
Dstrrchr.S32 cmpbge zero, t0, t1 # .. e1 : bits set iff byte == zero
38 andnot t1, t4, t1 # .. e1 : clear garbage from null test
40 bne t1, $eos # .. e1 : did we already hit the terminator?
49 cmpbge zero, t0, t1 # .. e1 : bits set iff byte == zero
51 beq t1, $loop # .. e1 : if we havnt seen a null, loop
55 negq t1, t4 # e0 : isolate first null byte match
56 and t1, t4, t4 # e1 :
73 and t8, 0xcc, t1 # .. e1 :
74 cmovne t1, t1, t8 # e0 :
75 cmovne t1, 2, t1 # .. e1 :
[all …]
Dev67-strlen_user.S61 lda t1, -1(zero) # E :
63 insqh t1, a0, t1 # U :
65 or t1, t0, t0 # E :
68 cmpbge zero, t0, t1 # E : t1 <- bitmask: bit i == 1 <==> i-th byte == 0
71 bne t1, $found # U :
84 cmpbge zero, t0, t1 # E :
87 beq t1, $loop # U :
89 $found: cttz t1, t2 # U0 :
Dev6-stxncpy.S67 mskqh t1, a1, t3 # U :
68 ornot t1, t2, t2 # E : (stall)
121 ldq_u t1, 0(a0) # L :
126 zap t1, t8, t1 # .. e1 : clear dst bytes <= null
127 or t0, t1, t0 # e1 : (stall)
153 xor a0, a1, t1 # E :
155 and t1, 7, t1 # E : (stall)
164 bne t1, $unaligned # U :
166 ldq_u t1, 0(a1) # L : load first src word
201 or t1, t4, t1 # E : first aligned src word complete (stall)
[all …]
Dev6-strncpy_from_user.S59 EX( ldq_u t1, 0(a1) ) # L : Latency=3 load first quadword
85 mskqh t1, a1, t3 # U :
87 ornot t1, t2, t2 # E :
140 ldq_u t1, 0(a0) # L :
145 zap t1, t8, t1 # U : clear dst bytes <= null
146 or t0, t1, t0 # E :
182 or t1, t4, t1 # E : first aligned src word complete
183 mskqh t1, a0, t1 # U : mask leading garbage in src
184 or t0, t1, t0 # E : first output word complete
205 extql t2, a1, t1 # U : position hi-bits of lo word
[all …]
/arch/alpha/include/asm/
Dswab.h26 __u64 t0, t1, t2, t3; in __arch_swab32() local
29 t1 = __kernel_inswl(x, 3); /* t1 : 000000CCDD000000 */ in __arch_swab32()
30 t1 |= t0; /* t1 : 000000CCDDAABBCC */ in __arch_swab32()
31 t2 = t1 >> 16; /* t2 : 0000000000CCDDAA */ in __arch_swab32()
32 t0 = t1 & 0xFF00FF00; /* t0 : 00000000DD00BB00 */ in __arch_swab32()
34 t1 = t0 + t3; /* t1 : ssssssssDDCCBBAA */ in __arch_swab32()
36 return t1; in __arch_swab32()
/arch/mips/include/asm/mach-pnx8550/
Dkernel-entry-init.h128 srl t1, t3, 19 /* C0_CONFIGPR_IL_SHIFT */
129 andi t1, t1, 0x7 /* C0_CONFIGPR_IL_MASK */
130 beq t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */
132 addiu t0, t1, 1
133 ori t1, zero, 1
134 sllv t1, t1, t0
156 addu t0, t0, t1 /* add bytes in a line */
166 move t1, zero
179 cache Index_Store_Tag_D, 0(t1)
182 addiu t1, t1, 32 /* 32 bytes in a line */
[all …]
/arch/mips/dec/
Dint-handler.S132 mfc0 t1,CP0_STATUS
137 and t0,t1 # isolate allowed ones
149 PTR_LA t1,cpu_mask_nr_tbl
150 1: lw t2,(t1)
154 addu t1,2*PTRSIZE # delay slot
159 lw a0,(-PTRSIZE)(t1)
178 andi t1,t0,KN02_IRQ_ALL
188 lw t1,IO_REG_SIMR(t2) # get mask: IOASIC simr
191 1: and t0,t1 # mask out allowed ones
198 PTR_LA t1,asic_mask_nr_tbl
[all …]
/arch/parisc/lib/
Dfixup.S28 .macro get_fault_ip t1 t2
30 LDREG RT%__per_cpu_offset(%r1),\t1
38 LDREGX \t2(\t1),\t2
40 LDREG RT%exception_data(%r1),\t1
42 add,l \t1,\t2,\t1
44 LDREG EXCDATA_IP(\t1), \t1
47 .macro get_fault_ip t1 t2
52 LDREG EXCDATA_IP(\t2), \t1
/arch/mips/lib/
Dmemset.S63 LONG_SLL t1, a1, 8
64 or a1, t1
65 LONG_SLL t1, a1, 16
67 or a1, t1
68 LONG_SLL t1, a1, 32
70 or a1, t1
99 1: ori t1, a2, 0x3f /* # of full blocks */
100 xori t1, 0x3f
101 beqz t1, .Lmemset_partial /* no block to fill */
104 PTR_ADDU t1, a0 /* end address */
[all …]
Dcsum_partial.S24 #undef t1
28 #define t1 $9 macro
155 lw t1, 0x04(src)
158 ADDC(sum, t1)
169 ld t1, 0x08(src)
171 ADDC(sum, t1)
173 CSUM_BIGCHUNK1(src, 0x00, sum, t0, t1, t3, t4)
184 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
185 CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
186 CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4)
[all …]
/arch/mips/include/asm/mach-ip27/
Dkernel-entry-init.h31 GET_NASID_ASM t1
32 move t2, t1 # text and data are here
40 GET_NASID_ASM t1
43 dsll t1, NASID_SHFT
44 or t0, t0, t1
46 lh t1, KV_RO_NASID_OFFSET(t0)
/arch/mips/alchemy/common/
Dsleeper.S59 la t1, __flush_cache_all
60 lw t0, 0(t1)
139 2: lw t1, 0x0850(a0) /* mem_sdstat */
140 and t2, t1, t0
147 lw t1, 0x0840(a0) /* mem_sdconfiga */
148 and t1, t0, t1 /* clear CE[1:0] */
149 sw t1, 0x0840(a0) /* mem_sdconfiga */
163 la t1, 4f
164 subu t2, t1, t0
199 li t1, (1 << 7 | 0x3F)
[all …]
/arch/ia64/lib/
Dcarta_random.S18 #define t1 r17 macro
25 pmpyshr2.u t1 = a, seed, 16
27 unpack2.l t0 = t1, t0
36 shr t1 = hi, 15 // t1 = (hi >> 15)
46 add lo = lo, t1

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