| /drivers/staging/rtl8723bs/hal/ |
| D | odm_interface.h | 26 #define _reg_all(_name) ODM_##_name argument
27 #define _reg_ic(_name, _ic) ODM_##_name##_ic argument
28 #define _bit_all(_name) BIT_##_name argument
29 #define _bit_ic(_name, _ic) BIT_##_name##_ic argument
39 #define _reg_11N(_name) ODM_REG_##_name##_11N argument
40 #define _bit_11N(_name) ODM_BIT_##_name##_11N argument
42 #define _cat(_name, _ic_type, _func) _func##_11N(_name) argument
47 #define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) argument
48 #define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) argument
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| /drivers/staging/rtlwifi/phydm/ |
| D | phydm_interface.h | 39 #define _reg_all(_name) ODM_##_name argument
40 #define _reg_ic(_name, _ic) ODM_##_name##_ic argument
41 #define _bit_all(_name) BIT_##_name argument
42 #define _bit_ic(_name, _ic) BIT_##_name##_ic argument
55 #define _reg_11N(_name) ODM_REG_##_name##_11N argument
56 #define _reg_11AC(_name) ODM_REG_##_name##_11AC argument
57 #define _bit_11N(_name) ODM_BIT_##_name##_11N argument
58 #define _bit_11AC(_name) ODM_BIT_##_name##_11AC argument
60 #define _cat(_name, _ic_type, _func) \ argument
69 #define ODM_REG(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _reg) argument
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| /drivers/clk/mvebu/ |
| D | armada-37xx-periph.c | 84 #define PERIPH_GATE(_name, _bit) \ argument
93 #define PERIPH_MUX(_name, _shift) \ argument
103 #define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \ argument
114 #define PERIPH_DIV(_name, _reg, _shift, _table) \ argument
124 #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\ argument
129 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \ argument
134 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \ argument
138 #define PERIPH_CLK_MUX_DIV(_name, _shift, _reg, _shift_div, _table) \ argument
142 #define PERIPH_CLK_MUX_DD(_name, _shift, _reg1, _reg2, _shift1, _shift2)\ argument
146 #define REF_CLK_FULL(_name) \ argument
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| /drivers/clk/zte/ |
| D | clk.h | 17 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
26 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
58 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ argument
73 #define ZX296718_PLL(_name, _parent, _reg, _table) \ argument
81 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
101 #define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \ argument
119 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ argument
135 #define MUX(_id, _name, _parent, _reg, _shift, _width) \ argument
143 #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \ argument
168 #define AUDIO_DIV(_id, _name, _parent, _reg) \ argument
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| /drivers/clk/mediatek/ |
| D | clk-mt8173.c | 630 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
669 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
678 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
745 #define GATE_IMG(_id, _name, _parent, _shift) { \ argument
776 #define GATE_MM0(_id, _name, _parent, _shift) { \ argument
785 #define GATE_MM1(_id, _name, _parent, _shift) { \ argument
863 #define GATE_VDEC0(_id, _name, _parent, _shift) { \ argument
872 #define GATE_VDEC1(_id, _name, _parent, _shift) { \ argument
886 #define GATE_VENC(_id, _name, _parent, _shift) { \ argument
902 #define GATE_VENCLT(_id, _name, _parent, _shift) { \ argument
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| D | clk-mt6797.c | 427 #define GATE_ICG0(_id, _name, _parent, _shift) { \ argument
436 #define GATE_ICG1(_id, _name, _parent, _shift) { \ argument
445 #define GATE_ICG2(_id, _name, _parent, _shift) { \ argument
604 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
624 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
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| D | clk-mtk.h | 36 #define FIXED_CLK(_id, _name, _parent, _rate) { \ argument
54 #define FACTOR(_id, _name, _parent, _mult, _div) { \ argument
90 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
109 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
113 #define MUX(_id, _name, _parents, _reg, _shift, _width) { \ argument
126 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ argument
179 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
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| D | clk-mt2701.c | 653 #define GATE_TOP_AUD(_id, _name, _parent, _shift) { \ argument
718 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
819 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
828 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
933 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
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| D | clk-mt8135.c | 411 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
448 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
457 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
604 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg,… argument
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| /drivers/clk/renesas/ |
| D | renesas-cpg-mssr.h | 46 #define DEF_TYPE(_name, _id, _type...) \ argument
48 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
51 #define DEF_INPUT(_name, _id) \ argument
53 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
55 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
57 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
75 #define DEF_MOD(_name, _mod, _parent...) \ argument
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| /drivers/regulator/ |
| D | mc13xxx.h | 59 #define MC13xxx_DEFINE(prefix, _name, _reg, _vsel_reg, _voltages, _ops) \ argument
77 #define MC13xxx_FIXED_DEFINE(prefix, _name, _reg, _voltages, _ops) \ argument
92 #define MC13xxx_GPO_DEFINE(prefix, _name, _reg, _voltages, _ops) \ argument
107 #define MC13xxx_DEFINE_SW(_name, _reg, _vsel_reg, _voltages, ops) \ argument
109 #define MC13xxx_DEFINE_REGU(_name, _reg, _vsel_reg, _voltages, ops) \ argument
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| D | pfuze100-regulator.c | 169 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \ argument
184 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \ argument
202 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \ argument
219 #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \ argument
239 #define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages) \ argument
256 #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \ argument
276 #define PFUZE3000_SW2_REG(_chip, _name, base, min, max, step) { \ argument
293 #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \ argument
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| /drivers/pinctrl/mvebu/ |
| D | pinctrl-mvebu.h | 137 #define MPP_FUNC_CTRL(_idl, _idh, _name, _func) \ argument
149 #define MPP_FUNC_GPIO_CTRL(_idl, _idh, _name, _func) \ argument
161 #define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
171 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
174 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
178 #define MPP_FUNCTION(_val, _name, _subname) \ argument
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| /drivers/clk/pistachio/ |
| D | clk.h | 22 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
42 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
62 #define DIV(_id, _name, _pname, _reg, _width) \ argument
72 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
89 #define FIXED_FACTOR(_id, _name, _pname, _div) \ argument
122 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument
133 #define PLL_FIXED(_id, _name, _pname, _type, _reg) \ argument
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| /drivers/clk/sunxi-ng/ |
| D | ccu_div.h | 95 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
112 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
119 #define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \ argument
138 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
147 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
157 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument
172 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ argument
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| D | ccu_mp.h | 39 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
58 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
87 #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
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| /drivers/usb/atm/ |
| D | cxacru.c | 212 #define CXACRU__ATTR_INIT(_name) \ argument
215 #define CXACRU_CMD_INIT(_name) \ argument
219 #define CXACRU_SET_INIT(_name) \ argument
223 #define CXACRU_ATTR_INIT(_value, _type, _name) \ argument
237 #define CXACRU_ATTR_CREATE(_v, _t, _name) CXACRU_DEVICE_CREATE_FILE(_name) argument
238 #define CXACRU_CMD_CREATE(_name) CXACRU_DEVICE_CREATE_FILE(_name) argument
239 #define CXACRU_SET_CREATE(_name) CXACRU_DEVICE_CREATE_FILE(_name) argument
240 #define CXACRU__ATTR_CREATE(_name) CXACRU_DEVICE_CREATE_FILE(_name) argument
242 #define CXACRU_ATTR_REMOVE(_v, _t, _name) CXACRU_DEVICE_REMOVE_FILE(_name) argument
243 #define CXACRU_CMD_REMOVE(_name) CXACRU_DEVICE_REMOVE_FILE(_name) argument
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| /drivers/clk/tegra/ |
| D | clk-tegra-periph.c | 147 #define MUX(_name, _parents, _offset, \ argument
154 #define MUX_FLAGS(_name, _parents, _offset,\ argument
161 #define MUX8(_name, _parents, _offset, \ argument
168 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
174 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \ argument
180 #define INT(_name, _parents, _offset, \ argument
187 #define INT_FLAGS(_name, _parents, _offset,\ argument
194 #define INT8(_name, _parents, _offset,\ argument
201 #define UART(_name, _parents, _offset,\ argument
208 #define UART8(_name, _parents, _offset,\ argument
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| /drivers/cpuidle/ |
| D | sysfs.c | 168 #define define_one_ro(_name, show) \ argument
170 #define define_one_rw(_name, show, store) \ argument
245 #define define_one_state_ro(_name, show) \ argument
248 #define define_one_state_rw(_name, show, store) \ argument
251 #define define_show_state_function(_name) \ argument
258 #define define_store_state_ull_function(_name) \ argument
277 #define define_show_state_ull_function(_name) \ argument
285 #define define_show_state_str_function(_name) \ argument
449 #define define_one_driver_ro(_name, show) \ argument
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| /drivers/s390/scsi/ |
| D | zfcp_sysfs.c | 16 #define ZFCP_DEV_ATTR(_feat, _name, _mode, _show, _store) \ argument
19 #define ZFCP_DEFINE_ATTR(_feat_def, _feat, _name, _format, _value) \ argument
31 #define ZFCP_DEFINE_ATTR_CONST(_feat, _name, _format, _value) \ argument
41 #define ZFCP_DEFINE_A_ATTR(_name, _format, _value) \ argument
420 #define ZFCP_DEFINE_LATENCY_ATTR(_name) \ argument
481 #define ZFCP_DEFINE_SCSI_ATTR(_name, _format, _value) \ argument
616 #define ZFCP_SHOST_ATTR(_name, _format, _arg...) \ argument
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| /drivers/staging/media/atomisp/include/media/ |
| D | lm3554.h | 30 #define v4l2_queryctrl_entry_integer(_id, _name,\ argument
43 #define v4l2_queryctrl_entry_boolean(_id, _name,\ argument
56 #define s_ctrl_id_entry_integer(_id, _name, \ argument
68 #define s_ctrl_id_entry_boolean(_id, _name, \ argument
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| D | lm3642.h | 28 #define v4l2_queryctrl_entry_integer(_id, _name,\ argument
41 #define v4l2_queryctrl_entry_boolean(_id, _name,\ argument
54 #define s_ctrl_id_entry_integer(_id, _name, \ argument
66 #define s_ctrl_id_entry_boolean(_id, _name, \ argument
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| /drivers/firmware/ |
| D | dcdbas.h | 57 #define DCDBAS_DEV_ATTR_RW(_name) \ argument
60 #define DCDBAS_DEV_ATTR_RO(_name) \ argument
63 #define DCDBAS_DEV_ATTR_WO(_name) \ argument
66 #define DCDBAS_BIN_ATTR_RW(_name) \ argument
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| /drivers/clk/qcom/ |
| D | clk-smd-rpm.c | 37 #define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id, \ argument
70 #define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, \ argument
105 #define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id) \ argument
109 #define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r) \ argument
113 #define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id) \ argument
117 #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id) \ argument
122 #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, r_id) \ argument
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| /drivers/mfd/ |
| D | lp8788.c | 23 #define MFD_DEV_SIMPLE(_name) \ argument
28 #define MFD_DEV_WITH_ID(_name, _id) \ argument
34 #define MFD_DEV_WITH_RESOURCE(_name, _resource, num_resource) \ argument
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