| /arch/mips/include/asm/sgi/ |
| D | mc.h | 17 u32 _unused0;
18 volatile u32 cpuctrl0; /* CPU control register 0, readwrite */
38 u32 _unused1;
39 volatile u32 cpuctrl1; /* CPU control register 1, readwrite */
48 u32 _unused2;
49 volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */
51 u32 _unused3;
52 volatile u32 systemid; /* MC system ID register, readonly */
56 u32 _unused4[3];
57 volatile u32 divider; /* Divider reg for RPSS */
[all …]
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| D | hpc3.h | 20 u32 pbuf; /* physical address of data buffer */
21 u32 cntinfo; /* counter and info bits */
33 u32 pnext; /* paddr of next hpc_dma_desc if any */
38 volatile u32 pbdma_bptr; /* pbus dma channel buffer ptr */
39 volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */
40 u32 _unused0[0x1000/4 - 2]; /* padding */
41 volatile u32 pbdma_ctrl; /* pbus dma channel control register has
58 u32 _unused1[0x1000/4 - 1]; /* padding */
63 volatile u32 cbptr; /* current dma buffer ptr, diagnostic use only */
64 volatile u32 ndptr; /* next dma descriptor ptr */
[all …]
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| /arch/mips/include/asm/mach-pmcs-msp71xx/ |
| D | msp_usb.h | 48 u32 id; /* 0x0: Identification register */
49 u32 hwgen; /* 0x4: General HW params */
50 u32 hwhost; /* 0x8: Host HW params */
51 u32 hwdev; /* 0xc: Device HW params */
52 u32 hwtxbuf; /* 0x10: Tx buffer HW params */
53 u32 hwrxbuf; /* 0x14: Rx buffer HW params */
54 u32 reserved[26];
55 u32 timer0_load; /* 0x80: General-purpose timer 0 load*/
56 u32 timer0_ctrl; /* 0x84: General-purpose timer 0 control */
57 u32 timer1_load; /* 0x88: General-purpose timer 1 load*/
[all …]
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| /arch/arm/include/asm/hardware/ |
| D | iop3xx.h | 39 #define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
50 #define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
55 #define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
56 #define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
57 #define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
58 #define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
59 #define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
60 #define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
63 #define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
68 #define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
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| /arch/powerpc/include/asm/ |
| D | mpc5121.h | 13 u32 rcwlr; /* Reset Configuration Word Low Register */
14 u32 rcwhr; /* Reset Configuration Word High Register */
15 u32 reserved1;
16 u32 reserved2;
17 u32 rsr; /* Reset Status Register */
18 u32 rmr; /* Reset Mode Register */
19 u32 rpr; /* Reset Protection Register */
20 u32 rcr; /* Reset Control Register */
21 u32 rcer; /* Reset Control Enable Register */
28 u32 spmr; /* System PLL Mode Register */
[all …]
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| D | immap_cpm2.h | 19 u32 sc_siumcr;
20 u32 sc_sypcr;
24 u32 sc_bcr;
27 u32 sc_ppc_alrh;
28 u32 sc_ppc_alrl;
31 u32 sc_lcl_alrh;
32 u32 sc_lcl_alrl;
33 u32 sc_tescr1;
34 u32 sc_tescr2;
35 u32 sc_ltescr1;
[all …]
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| D | mpc52xx.h | 38 u32 mbar; /* MMAP_CTRL + 0x00 */
40 u32 cs0_start; /* MMAP_CTRL + 0x04 */
41 u32 cs0_stop; /* MMAP_CTRL + 0x08 */
42 u32 cs1_start; /* MMAP_CTRL + 0x0c */
43 u32 cs1_stop; /* MMAP_CTRL + 0x10 */
44 u32 cs2_start; /* MMAP_CTRL + 0x14 */
45 u32 cs2_stop; /* MMAP_CTRL + 0x18 */
46 u32 cs3_start; /* MMAP_CTRL + 0x1c */
47 u32 cs3_stop; /* MMAP_CTRL + 0x20 */
48 u32 cs4_start; /* MMAP_CTRL + 0x24 */
[all …]
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| D | cell-pmu.h | 79 extern u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);
80 extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
81 extern u32 cbe_read_ctr(u32 cpu, u32 ctr);
82 extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
84 extern u32 cbe_read_pm07_control(u32 cpu, u32 ctr);
85 extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
86 extern u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg);
87 extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
89 extern u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr);
90 extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
[all …]
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| D | pmac_pfunc.h | 26 u32 v;
27 u32 *p;
67 int (*write_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask);
68 int (*read_reg32)(PMF_STD_ARGS, u32 offset);
69 int (*write_reg16)(PMF_STD_ARGS, u32 offset, u16 value, u16 mask);
70 int (*read_reg16)(PMF_STD_ARGS, u32 offset);
71 int (*write_reg8)(PMF_STD_ARGS, u32 offset, u8 value, u8 mask);
72 int (*read_reg8)(PMF_STD_ARGS, u32 offset);
74 int (*delay)(PMF_STD_ARGS, u32 duration);
76 int (*wait_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask);
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| D | kvm_fpu.h | 25 extern void fps_fres(u64 *fpscr, u32 *dst, u32 *src1);
26 extern void fps_frsqrte(u64 *fpscr, u32 *dst, u32 *src1);
27 extern void fps_fsqrts(u64 *fpscr, u32 *dst, u32 *src1);
29 extern void fps_fadds(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2);
30 extern void fps_fdivs(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2);
31 extern void fps_fmuls(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2);
32 extern void fps_fsubs(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2);
34 extern void fps_fmadds(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2,
35 u32 *src3);
36 extern void fps_fmsubs(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2,
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| /arch/s390/include/asm/ |
| D | css_chars.h | 9 u32 dynio : 1; /* bit 12 */
10 u32 : 4;
11 u32 eadm : 1; /* bit 17 */
12 u32 : 23;
13 u32 aif : 1; /* bit 41 */
14 u32 : 3;
15 u32 mcss : 1; /* bit 45 */
16 u32 fcs : 1; /* bit 46 */
17 u32 : 1;
18 u32 ext_mb : 1; /* bit 48 */
[all …]
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| D | fcx.h | 38 u32 format:2;
39 u32 :6;
40 u32 flags:24;
41 u32 :8;
42 u32 tccbl:6;
43 u32 r:1;
44 u32 w:1;
45 u32 :16;
50 u32 output_count;
51 u32 input_count;
[all …]
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| /arch/microblaze/include/asm/ |
| D | cpuinfo.h | 35 u32 use_instr;
36 u32 use_mult;
37 u32 use_fpu;
38 u32 use_exc;
39 u32 ver_code;
40 u32 mmu;
41 u32 mmu_privins;
42 u32 endian;
45 u32 use_icache;
46 u32 icache_tagbits;
[all …]
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| /arch/arm/mach-omap2/ |
| D | omap-secure.h | 64 extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
65 u32 arg1, u32 arg2, u32 arg3, u32 arg4);
66 extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
67 extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs);
70 extern u32 save_secure_ram_context(u32 args_pa);
71 extern u32 omap3_save_secure_ram(void __iomem *save_regs, int size);
73 extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
74 u32 arg1, u32 arg2, u32 arg3, u32 arg4);
75 extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
76 extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);
|
| D | sram.h | 12 extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
13 u32 base_cs, u32 force_unlock);
14 extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
15 u32 mem_type);
16 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
21 extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
24 extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
25 u32 base_cs, u32 force_unlock);
28 extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
32 extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
[all …]
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| D | omap-secure.c | 37 u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2, in omap_secure_dispatcher()
38 u32 arg3, u32 arg4) in omap_secure_dispatcher()
40 u32 ret; in omap_secure_dispatcher()
41 u32 param[5]; in omap_secure_dispatcher()
63 u32 size = OMAP_SECURE_RAM_STORAGE; in omap_secure_ram_reserve_memblock()
77 u32 omap3_save_secure_ram(void __iomem *addr, int size) in omap3_save_secure_ram()
79 u32 ret; in omap3_save_secure_ram()
80 u32 param[5]; in omap3_save_secure_ram()
110 u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, in rx51_secure_dispatcher()
111 u32 arg1, u32 arg2, u32 arg3, u32 arg4) in rx51_secure_dispatcher()
[all …]
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| /arch/x86/include/asm/ |
| D | intel_pmc_ipc.h | 35 int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
36 u32 *out, u32 outlen, u32 dptr, u32 sptr);
37 int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
38 u32 *out, u32 outlen);
40 int intel_pmc_gcr_read(u32 offset, u32 *data);
41 int intel_pmc_gcr_write(u32 offset, u32 data);
42 int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val);
51 static inline int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, in intel_pmc_ipc_raw_cmd()
52 u32 *out, u32 outlen, u32 dptr, u32 sptr) in intel_pmc_ipc_raw_cmd()
57 static inline int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen, in intel_pmc_ipc_command()
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| D | apicdef.h | 177 #define u32 unsigned int macro
181 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
183 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
186 u32 __reserved_1 : 24,
189 u32 __reserved[3];
194 u32 version : 8,
198 u32 __reserved[3];
201 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
203 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
205 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
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| /arch/mips/include/asm/mach-rc32434/ |
| D | eth.h | 36 u32 ethintfc;
37 u32 ethfifott;
38 u32 etharc;
39 u32 ethhash0;
40 u32 ethhash1;
41 u32 ethu0[4]; /* Reserved. */
42 u32 ethpfs;
43 u32 ethmcp;
44 u32 eth_u1[10]; /* Reserved. */
45 u32 ethspare;
[all …]
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| /arch/mips/include/asm/txx9/ |
| D | tx4927pcic.h | 16 u32 pciid;
17 u32 pcistatus;
18 u32 pciccrev;
19 u32 pcicfg1;
20 u32 p2gm0plbase; /* +10 */
21 u32 p2gm0pubase;
22 u32 p2gm1plbase;
23 u32 p2gm1pubase;
24 u32 p2gm2pbase; /* +20 */
25 u32 p2giopbase;
[all …]
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| /arch/powerpc/sysdev/ |
| D | fsl_85xx_cache_ctlr.h | 51 u32 ctl; /* 0x000 - L2 control */
53 u32 ewar0; /* 0x010 - External write address 0 */
54 u32 ewarea0; /* 0x014 - External write address extended 0 */
55 u32 ewcr0; /* 0x018 - External write ctrl */
57 u32 ewar1; /* 0x020 - External write address 1 */
58 u32 ewarea1; /* 0x024 - External write address extended 1 */
59 u32 ewcr1; /* 0x028 - External write ctrl 1 */
61 u32 ewar2; /* 0x030 - External write address 2 */
62 u32 ewarea2; /* 0x034 - External write address extended 2 */
63 u32 ewcr2; /* 0x038 - External write ctrl 2 */
[all …]
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| /arch/arm/mach-ixp4xx/include/mach/ |
| D | ixp46x_ts.h | 28 u32 ch_control; /* 0x40 Time Synchronization Channel Control */
29 u32 ch_event; /* 0x44 Time Synchronization Channel Event */
30 u32 tx_snap_lo; /* 0x48 Transmit Snapshot Low Register */
31 u32 tx_snap_hi; /* 0x4C Transmit Snapshot High Register */
32 u32 rx_snap_lo; /* 0x50 Receive Snapshot Low Register */
33 u32 rx_snap_hi; /* 0x54 Receive Snapshot High Register */
34 u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
35 u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
39 u32 control; /* 0x00 Time Sync Control Register */
40 u32 event; /* 0x04 Time Sync Event Register */
[all …]
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| /arch/x86/kvm/ |
| D | tss.h | 6 u32 prev_task_link;
7 u32 esp0;
8 u32 ss0;
9 u32 esp1;
10 u32 ss1;
11 u32 esp2;
12 u32 ss2;
13 u32 cr3;
14 u32 eip;
15 u32 eflags;
[all …]
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| /arch/mips/include/asm/mach-au1x00/ |
| D | au1xxx_dbdma.h | 41 u32 ddma_config;
42 u32 ddma_intstat;
43 u32 ddma_throttle;
44 u32 ddma_inten;
56 u32 ddma_cfg; /* See below */
57 u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
58 u32 ddma_statptr; /* word aligned pointer to status word */
59 u32 ddma_dbell; /* A write activates channel operation */
60 u32 ddma_irq; /* If bit 0 set, interrupt pending */
61 u32 ddma_stat; /* See below */
[all …]
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| /arch/mips/include/asm/sn/ |
| D | ioc3.h | 72 volatile u32 pad0[7]; /* 0x00000 */
73 volatile u32 sio_ir; /* 0x0001c */
74 volatile u32 sio_ies; /* 0x00020 */
75 volatile u32 sio_iec; /* 0x00024 */
76 volatile u32 sio_cr; /* 0x00028 */
77 volatile u32 int_out; /* 0x0002c */
78 volatile u32 mcr; /* 0x00030 */
81 volatile u32 gpcr_s; /* 0x00034 */
82 volatile u32 gpcr_c; /* 0x00038 */
83 volatile u32 gpdr; /* 0x0003c */
[all …]
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