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Searched refs:INTEL_GEN (Results 1 – 25 of 51) sorted by relevance

123

/drivers/gpu/drm/i915/
Di915_suspend.c35 if (INTEL_GEN(dev_priv) <= 4) in i915_save_display()
39 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) in i915_save_display()
46 if (INTEL_GEN(dev_priv) <= 4) in i915_restore_display()
53 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) in i915_restore_display()
73 if (INTEL_GEN(dev_priv) < 7) in i915_save_state()
119 if (INTEL_GEN(dev_priv) < 7) in i915_restore_state()
Dintel_fbc.c51 return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8; in fbc_on_pipe_a_only()
56 return INTEL_GEN(dev_priv) < 4; in fbc_on_plane_a_only()
61 return INTEL_GEN(dev_priv) <= 3; in no_fbc_on_multiple_pipes()
97 if (INTEL_GEN(dev_priv) == 7) in intel_fbc_calculate_cfb_size()
99 else if (INTEL_GEN(dev_priv) >= 8) in intel_fbc_calculate_cfb_size()
347 if (INTEL_GEN(dev_priv) >= 5) in intel_fbc_hw_is_active()
361 if (INTEL_GEN(dev_priv) >= 7) in intel_fbc_hw_activate()
363 else if (INTEL_GEN(dev_priv) >= 5) in intel_fbc_hw_activate()
377 if (INTEL_GEN(dev_priv) >= 5) in intel_fbc_hw_deactivate()
556 if (ret && INTEL_GEN(dev_priv) <= 4) { in find_compression_threshold()
[all …]
Dintel_ringbuffer.c390 if (INTEL_GEN(dev_priv) >= 4) in ring_setup_phys_status_page()
461 if (INTEL_GEN(dev_priv) > 2) { in stop_ring()
483 if (INTEL_GEN(dev_priv) > 2) { in stop_ring()
1614 WARN_ON(INTEL_GEN(dev_priv) > 2 && in intel_engine_cleanup()
1844 if (INTEL_GEN(req->i915) >= 8) in gen6_bsd_ring_flush()
1865 if (INTEL_GEN(req->i915) >= 8) { in gen6_bsd_ring_flush()
1953 if (INTEL_GEN(req->i915) >= 8) in gen6_ring_flush()
1973 if (INTEL_GEN(req->i915) >= 8) { in gen6_ring_flush()
1994 if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore) { in intel_ring_init_semaphores()
2016 if (INTEL_GEN(dev_priv) >= 8) { in intel_ring_init_semaphores()
[all …]
Dintel_hangcheck.c30 if (INTEL_GEN(engine->i915) >= 8) { in ipehr_is_semaphore_wait()
47 if (INTEL_GEN(dev_priv) >= 8) { in semaphore_wait_to_signaller_ring()
115 backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4; in semaphore_waits_for()
138 if (INTEL_GEN(dev_priv) >= 8) { in semaphore_waits_for()
276 if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) { in engine_stuck()
Di915_gpu_error.c353 if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3) in error_print_instdone()
359 if (INTEL_GEN(m->i915) <= 6) in error_print_instdone()
422 if (INTEL_GEN(m->i915) >= 4) { in error_print_engine()
431 if (INTEL_GEN(m->i915) >= 6) { in error_print_engine()
445 if (INTEL_GEN(m->i915) >= 8) { in error_print_engine()
652 if (INTEL_GEN(dev_priv) >= 6) { in i915_error_state_to_str()
655 if (INTEL_GEN(dev_priv) >= 8) in i915_error_state_to_str()
1035 if (INTEL_GEN(dev_priv) >= 6) { in i915_gem_record_fences()
1038 } else if (INTEL_GEN(dev_priv) >= 4) { in i915_gem_record_fences()
1168 if (INTEL_GEN(dev_priv) >= 6) { in error_record_engine_registers()
[all …]
Di915_debugfs.c61 seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); in i915_capabilities()
735 } else if (INTEL_GEN(dev_priv) >= 8) { in i915_interrupt_info()
873 if (INTEL_GEN(dev_priv) >= 6) { in i915_interrupt_info()
1070 } else if (INTEL_GEN(dev_priv) >= 6) { in i915_frequency_info()
1094 if (INTEL_GEN(dev_priv) >= 9) in i915_frequency_info()
1116 if (INTEL_GEN(dev_priv) >= 9) in i915_frequency_info()
1145 (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8); in i915_frequency_info()
1232 if (INTEL_GEN(dev_priv) <= 3) in i915_instdone_info()
1238 if (INTEL_GEN(dev_priv) <= 6) in i915_instdone_info()
1500 if (INTEL_GEN(dev_priv) >= 9) { in gen6_drpc_info()
[all …]
Di915_gem_tiling.c83 if (INTEL_GEN(i915) >= 4) { in i915_gem_fence_size()
123 if (INTEL_GEN(i915) >= 4) in i915_gem_fence_alignment()
151 if (INTEL_GEN(i915) >= 7) { in i915_tiling_ok()
154 } else if (INTEL_GEN(i915) >= 4) { in i915_tiling_ok()
Di915_irq.c278 return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; in gen6_pm_iir()
283 return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; in gen6_pm_imr()
288 return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; in gen6_pm_ier()
658 if (INTEL_GEN(dev_priv) >= 4) in i915_enable_asle_pipestat()
875 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { in i915_get_crtc_scanoutpos()
935 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { in i915_get_crtc_scanoutpos()
1630 if (INTEL_GEN(dev_priv) >= 3) in i9xx_pipe_crc_irq_handler()
1635 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_pipe_crc_irq_handler()
1662 if (INTEL_GEN(dev_priv) >= 8) in gen6_rps_irq_handler()
2358 if (INTEL_GEN(dev_priv) >= 6) in ironlake_irq_handler()
[all …]
Dintel_engine_cs.c149 switch (INTEL_GEN(dev_priv)) { in __intel_engine_context_size()
151 MISSING_CASE(INTEL_GEN(dev_priv)); in __intel_engine_context_size()
184 if (INTEL_GEN(dev_priv) < 8) in __intel_engine_context_size()
513 if (INTEL_GEN(dev_priv) >= 8) in intel_engine_get_active_head()
516 else if (INTEL_GEN(dev_priv) >= 4) in intel_engine_get_active_head()
529 if (INTEL_GEN(dev_priv) >= 8) in intel_engine_get_last_batch_head()
598 switch (INTEL_GEN(dev_priv)) { in intel_engine_get_instdone()
1256 if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE)) in ring_is_idle()
Dintel_sprite.c938 if (INTEL_GEN(dev_priv) >= 9) { in intel_check_sprite_plane()
1054 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 || in intel_check_sprite_plane()
1073 if (INTEL_GEN(dev_priv) >= 9) { in intel_check_sprite_plane()
1085 } else if (INTEL_GEN(dev_priv) >= 7) { in intel_check_sprite_plane()
1300 if (INTEL_GEN(dev_priv) >= 9) in intel_sprite_plane_format_mod_supported()
1347 if (INTEL_GEN(dev_priv) >= 10) { in intel_sprite_plane_create()
1358 } else if (INTEL_GEN(dev_priv) >= 9) { in intel_sprite_plane_create()
1380 } else if (INTEL_GEN(dev_priv) >= 7) { in intel_sprite_plane_create()
1414 if (INTEL_GEN(dev_priv) >= 9) { in intel_sprite_plane_create()
1435 if (INTEL_GEN(dev_priv) >= 9) in intel_sprite_plane_create()
Dintel_display.c1064 if (INTEL_GEN(dev_priv) >= 4) { in intel_wait_for_pipe_off()
1560 if (INTEL_GEN(dev_priv) >= 4) { in i9xx_enable_pll()
2097 if (INTEL_GEN(dev_priv) >= 9) in intel_surf_alignment()
3173 if (INTEL_GEN(dev_priv) < 4) in i9xx_plane_ctl()
3203 if (INTEL_GEN(dev_priv) >= 4 && in i9xx_plane_ctl()
3226 if (INTEL_GEN(dev_priv) >= 4) in i9xx_check_plane_surface()
3270 if (INTEL_GEN(dev_priv) >= 4) in i9xx_update_primary_plane()
3280 if (INTEL_GEN(dev_priv) < 4) { in i9xx_update_primary_plane()
3304 } else if (INTEL_GEN(dev_priv) >= 4) { in i9xx_update_primary_plane()
3674 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); in gpu_reset_clobbers_display()
[all …]
Di915_gem_context.c578 (i915.semaphores && INTEL_GEN(dev_priv) == 7) ? in mi_set_context()
585 if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) in mi_set_context()
592 if (INTEL_GEN(dev_priv) >= 7) in mi_set_context()
600 if (INTEL_GEN(dev_priv) >= 7) { in mi_set_context()
627 if (INTEL_GEN(dev_priv) >= 7) { in mi_set_context()
721 if (INTEL_GEN(engine->i915) < 8) in needs_pd_load_pre()
Di915_gem_stolen.c101 if (INTEL_GEN(dev_priv) >= 3) { in i915_stolen_to_dma()
196 if (INTEL_GEN(dev_priv) <= 4 && in i915_stolen_to_dma()
418 if (intel_vtd_active() && INTEL_GEN(dev_priv) < 8) { in i915_gem_init_stolen()
495 if (INTEL_GEN(dev_priv) >= 8) in i915_gem_init_stolen()
Dintel_pm.c2571 if (INTEL_GEN(dev_priv) >= 8) in ilk_display_fifo_size()
2573 else if (INTEL_GEN(dev_priv) >= 7) in ilk_display_fifo_size()
2583 if (INTEL_GEN(dev_priv) >= 8) in ilk_plane_wm_reg_max()
2586 else if (INTEL_GEN(dev_priv) >= 7) in ilk_plane_wm_reg_max()
2600 if (INTEL_GEN(dev_priv) >= 7) in ilk_cursor_wm_reg_max()
2608 if (INTEL_GEN(dev_priv) >= 8) in ilk_fbc_wm_reg_max()
2637 if (INTEL_GEN(dev_priv) <= 6) in ilk_plane_wm_max()
2798 if (INTEL_GEN(dev_priv) >= 9) { in intel_read_wm_latency()
2883 } else if (INTEL_GEN(dev_priv) >= 6) { in intel_read_wm_latency()
2890 } else if (INTEL_GEN(dev_priv) >= 5) { in intel_read_wm_latency()
[all …]
Dintel_lvds.c138 if (INTEL_GEN(dev_priv) < 5) in intel_lvds_get_config()
143 if (INTEL_GEN(dev_priv) < 4) { in intel_lvds_get_config()
396 if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { in intel_lvds_compute_config()
821 if (INTEL_GEN(dev_priv) <= 4 && in intel_lvds_supported()
Di915_gem_gtt.c159 if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9) in intel_sanitize_enable_ppgtt()
163 if (enable_ppgtt == 1 && INTEL_GEN(dev_priv) != 9) in intel_sanitize_enable_ppgtt()
184 if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) { in intel_sanitize_enable_ppgtt()
1921 else if (INTEL_GEN(dev_priv) >= 8) in i915_ppgtt_init_hw()
1924 MISSING_CASE(INTEL_GEN(dev_priv)); in i915_ppgtt_init_hw()
2043 if (INTEL_GEN(dev_priv) < 6) in i915_gem_suspend_gtt_mappings()
2875 if (INTEL_GEN(dev_priv) >= 9) { in gen8_gmch_probe()
2888 if (INTEL_GEN(dev_priv) >= 10) in gen8_gmch_probe()
2964 else if (INTEL_GEN(dev_priv) >= 7) in gen6_gmch_probe()
3021 if (INTEL_GEN(dev_priv) <= 5) in i915_ggtt_probe_hw()
[all …]
Dintel_device_info.c317 if (INTEL_GEN(dev_priv) >= 9) { in intel_device_info_runtime_init()
341 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { in intel_device_info_runtime_init()
Dintel_lrc.c239 if (INTEL_GEN(dev_priv) >= 9) in intel_sanitize_enable_execlists()
1201 switch (INTEL_GEN(engine->i915)) { in intel_init_workaround_bb()
1211 MISSING_CASE(INTEL_GEN(engine->i915)); in intel_init_workaround_bb()
1841 if (INTEL_GEN(dev_priv) >= 9) in logical_render_ring_init()
1884 if (INTEL_GEN(dev_priv) < 9) in make_rpcs()
1922 switch (INTEL_GEN(engine->i915)) { in intel_lr_indirect_ctx_offset()
1924 MISSING_CASE(INTEL_GEN(engine->i915)); in intel_lr_indirect_ctx_offset()
Dintel_uncore.c319 if (INTEL_GEN(dev_priv) < 9) in intel_uncore_edram_size()
329 INTEL_GEN(dev_priv) >= 9) { in intel_uncore_edram_detect()
652 (INTEL_GEN(dev_priv) >= 9 || \
1067 if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv)) in intel_uncore_fw_domains_init()
1081 if (INTEL_GEN(dev_priv) >= 9) { in intel_uncore_fw_domains_init()
1788 } else if (INTEL_GEN(dev_priv) >= 6) { in intel_uncore_forcewake_for_read()
Di915_drv.c434 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_alloc_mchbar_resource()
439 if (INTEL_GEN(dev_priv) >= 4) in intel_alloc_mchbar_resource()
466 if (INTEL_GEN(dev_priv) >= 4) in intel_alloc_mchbar_resource()
479 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_setup_mchbar()
518 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_teardown_mchbar()
953 if (INTEL_GEN(dev_priv) < 5) in i915_mmio_setup()
1153 if (INTEL_GEN(dev_priv) >= 5) { in i915_driver_init_hw()
1610 if (!(hibernation && INTEL_GEN(dev_priv) < 6)) in i915_drm_suspend_late()
Dintel_crt.c155 if (INTEL_GEN(dev_priv) >= 5) in intel_crt_set_dpms()
730 else if (INTEL_GEN(dev_priv) < 4) in intel_crt_detect()
785 if (INTEL_GEN(dev_priv) >= 5) { in intel_crt_reset()
/drivers/gpu/drm/i915/selftests/
Di915_gem_object.c365 if (INTEL_GEN(i915) <= 2) { in igt_partial_tiling()
380 if (INTEL_GEN(i915) < 4) in igt_partial_tiling()
382 else if (INTEL_GEN(i915) < 7) in igt_partial_tiling()
395 if (pitch > 2 && INTEL_GEN(i915) >= 4) { in igt_partial_tiling()
404 if (pitch < max_pitch && INTEL_GEN(i915) >= 4) { in igt_partial_tiling()
414 if (INTEL_GEN(i915) >= 4) { in igt_partial_tiling()
Dintel_hangcheck.c138 if (INTEL_GEN(i915) >= 8) { in emit_recurse_batch()
146 } else if (INTEL_GEN(i915) >= 6) { in emit_recurse_batch()
153 } else if (INTEL_GEN(i915) >= 4) { in emit_recurse_batch()
170 if (INTEL_GEN(vm->i915) <= 5) in emit_recurse_batch()
Di915_gem_coherency.c207 if (INTEL_GEN(i915) >= 8) { in gpu_set()
212 } else if (INTEL_GEN(i915) >= 4) { in gpu_set()
Dintel_uncore.c173 INTEL_GEN(i915) >= 9); in intel_uncore_live_selftests()

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