| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_device.c | 65 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
66 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
67 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev);
95 struct amdgpu_device *adev = dev->dev_private; in amdgpu_device_is_px() local
97 if (adev->flags & AMD_IS_PX) in amdgpu_device_is_px()
105 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, in amdgpu_mm_rreg() argument
110 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { in amdgpu_mm_rreg()
112 return amdgpu_virt_kiq_rreg(adev, reg); in amdgpu_mm_rreg()
115 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) in amdgpu_mm_rreg()
116 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); in amdgpu_mm_rreg()
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| D | amdgpu_dpm.h | 245 int (*get_temperature)(struct amdgpu_device *adev);
246 int (*pre_set_power_state)(struct amdgpu_device *adev);
247 int (*set_power_state)(struct amdgpu_device *adev);
248 void (*post_set_power_state)(struct amdgpu_device *adev);
249 void (*display_configuration_changed)(struct amdgpu_device *adev);
250 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
251 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
252 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
253 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
254 int (*force_performance_level)(struct amdgpu_device *adev, enum amd_dpm_forced_level level);
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| D | gmc_v9_0.c | 74 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, in gmc_v9_0_vm_fault_interrupt_state() argument
93 hub = &adev->vmhub[AMDGPU_MMHUB]; in gmc_v9_0_vm_fault_interrupt_state()
102 hub = &adev->vmhub[AMDGPU_GFXHUB]; in gmc_v9_0_vm_fault_interrupt_state()
112 hub = &adev->vmhub[AMDGPU_MMHUB]; in gmc_v9_0_vm_fault_interrupt_state()
121 hub = &adev->vmhub[AMDGPU_GFXHUB]; in gmc_v9_0_vm_fault_interrupt_state()
136 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, in gmc_v9_0_process_interrupt() argument
140 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vm_id_src]; in gmc_v9_0_process_interrupt()
147 if (!amdgpu_sriov_vf(adev)) { in gmc_v9_0_process_interrupt()
153 dev_err(adev->dev, in gmc_v9_0_process_interrupt()
158 dev_err(adev->dev, " at page 0x%016llx from %d\n", in gmc_v9_0_process_interrupt()
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| D | vi.c | 84 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) in vi_pcie_rreg() argument
89 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
93 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
97 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_pcie_wreg() argument
101 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
106 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
109 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) in vi_smc_rreg() argument
114 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_smc_rreg()
117 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in vi_smc_rreg()
121 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_smc_wreg() argument
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| D | soc15.c | 100 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) in soc15_pcie_rreg() argument
106 if (adev->flags & AMD_IS_APU) in soc15_pcie_rreg()
114 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in soc15_pcie_rreg()
118 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in soc15_pcie_rreg()
122 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_pcie_wreg() argument
127 if (adev->flags & AMD_IS_APU) in soc15_pcie_wreg()
135 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in soc15_pcie_wreg()
140 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in soc15_pcie_wreg()
143 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) in soc15_uvd_ctx_rreg() argument
151 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
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| D | amdgpu_ih.c | 37 static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev) in amdgpu_ih_ring_alloc() argument
42 if (adev->irq.ih.ring_obj == NULL) { in amdgpu_ih_ring_alloc()
43 r = amdgpu_bo_create_kernel(adev, adev->irq.ih.ring_size, in amdgpu_ih_ring_alloc()
45 &adev->irq.ih.ring_obj, in amdgpu_ih_ring_alloc()
46 &adev->irq.ih.gpu_addr, in amdgpu_ih_ring_alloc()
47 (void **)&adev->irq.ih.ring); in amdgpu_ih_ring_alloc()
65 int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size, in amdgpu_ih_ring_init() argument
74 adev->irq.ih.ring_size = ring_size; in amdgpu_ih_ring_init()
75 adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1; in amdgpu_ih_ring_init()
76 adev->irq.ih.rptr = 0; in amdgpu_ih_ring_init()
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| D | amdgpu_pm.c | 35 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
65 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) in amdgpu_pm_acpi_event_handler() argument
67 if (adev->pp_enabled) in amdgpu_pm_acpi_event_handler()
71 if (adev->pm.dpm_enabled) { in amdgpu_pm_acpi_event_handler()
72 mutex_lock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
74 adev->pm.dpm.ac_power = true; in amdgpu_pm_acpi_event_handler()
76 adev->pm.dpm.ac_power = false; in amdgpu_pm_acpi_event_handler()
77 if (adev->pm.funcs->enable_bapm) in amdgpu_pm_acpi_event_handler()
78 amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power); in amdgpu_pm_acpi_event_handler()
79 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
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| D | amdgpu_gart.c | 69 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev) in amdgpu_gart_table_ram_alloc() argument
73 ptr = pci_alloc_consistent(adev->pdev, adev->gart.table_size, in amdgpu_gart_table_ram_alloc()
74 &adev->gart.table_addr); in amdgpu_gart_table_ram_alloc()
81 adev->gart.table_size >> PAGE_SHIFT); in amdgpu_gart_table_ram_alloc()
84 adev->gart.ptr = ptr; in amdgpu_gart_table_ram_alloc()
85 memset((void *)adev->gart.ptr, 0, adev->gart.table_size); in amdgpu_gart_table_ram_alloc()
98 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) in amdgpu_gart_table_ram_free() argument
100 if (adev->gart.ptr == NULL) { in amdgpu_gart_table_ram_free()
105 set_memory_wb((unsigned long)adev->gart.ptr, in amdgpu_gart_table_ram_free()
106 adev->gart.table_size >> PAGE_SHIFT); in amdgpu_gart_table_ram_free()
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| D | amdgpu_powerplay.c | 37 static int amdgpu_create_pp_handle(struct amdgpu_device *adev) in amdgpu_create_pp_handle() argument
43 amd_pp = &(adev->powerplay); in amdgpu_create_pp_handle()
44 pp_init.chip_family = adev->family; in amdgpu_create_pp_handle()
45 pp_init.chip_id = adev->asic_type; in amdgpu_create_pp_handle()
46 pp_init.pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false; in amdgpu_create_pp_handle()
48 pp_init.device = amdgpu_cgs_create_device(adev); in amdgpu_create_pp_handle()
57 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in amdgpu_pp_early_init() local
61 amd_pp = &(adev->powerplay); in amdgpu_pp_early_init()
62 adev->pp_enabled = false; in amdgpu_pp_early_init()
63 amd_pp->pp_handle = (void *)adev; in amdgpu_pp_early_init()
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| D | kv_dpm.c | 45 static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev);
46 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
47 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
49 static void kv_init_graphics_levels(struct amdgpu_device *adev);
50 static int kv_calculate_ds_divider(struct amdgpu_device *adev);
51 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
52 static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
53 static void kv_enable_new_levels(struct amdgpu_device *adev);
54 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
56 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
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| D | gmc_v6_0.c | 39 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
40 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
69 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev) in gmc_v6_0_mc_stop() argument
73 gmc_v6_0_wait_for_idle((void *)adev); in gmc_v6_0_mc_stop()
89 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev) in gmc_v6_0_mc_resume() argument
103 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) in gmc_v6_0_init_microcode() argument
112 switch (adev->asic_type) { in gmc_v6_0_init_microcode()
139 err = request_firmware(&adev->mc.fw, fw_name, adev->dev); in gmc_v6_0_init_microcode()
143 err = amdgpu_ucode_validate(adev->mc.fw); in gmc_v6_0_init_microcode()
147 dev_err(adev->dev, in gmc_v6_0_init_microcode()
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| D | gmc_v8_0.c | 47 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
48 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
122 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) in gmc_v8_0_init_golden_registers() argument
124 switch (adev->asic_type) { in gmc_v8_0_init_golden_registers()
126 amdgpu_program_register_sequence(adev, in gmc_v8_0_init_golden_registers()
129 amdgpu_program_register_sequence(adev, in gmc_v8_0_init_golden_registers()
134 amdgpu_program_register_sequence(adev, in gmc_v8_0_init_golden_registers()
137 amdgpu_program_register_sequence(adev, in gmc_v8_0_init_golden_registers()
143 amdgpu_program_register_sequence(adev, in gmc_v8_0_init_golden_registers()
148 amdgpu_program_register_sequence(adev, in gmc_v8_0_init_golden_registers()
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| D | tonga_ih.c | 49 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev);
58 static void tonga_ih_enable_interrupts(struct amdgpu_device *adev) in tonga_ih_enable_interrupts() argument
65 adev->irq.ih.enabled = true; in tonga_ih_enable_interrupts()
75 static void tonga_ih_disable_interrupts(struct amdgpu_device *adev) in tonga_ih_disable_interrupts() argument
85 adev->irq.ih.enabled = false; in tonga_ih_disable_interrupts()
86 adev->irq.ih.rptr = 0; in tonga_ih_disable_interrupts()
100 static int tonga_ih_irq_init(struct amdgpu_device *adev) in tonga_ih_irq_init() argument
107 tonga_ih_disable_interrupts(adev); in tonga_ih_irq_init()
110 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8); in tonga_ih_irq_init()
121 if (adev->irq.ih.use_bus_addr) in tonga_ih_irq_init()
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| D | cik.c | 75 static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg) in cik_pcie_rreg() argument
80 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in cik_pcie_rreg()
84 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in cik_pcie_rreg()
88 static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in cik_pcie_wreg() argument
92 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in cik_pcie_wreg()
97 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in cik_pcie_wreg()
100 static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg) in cik_smc_rreg() argument
105 spin_lock_irqsave(&adev->smc_idx_lock, flags); in cik_smc_rreg()
108 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in cik_smc_rreg()
112 static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in cik_smc_wreg() argument
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| D | amdgpu_irq.c | 58 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, in amdgpu_hotplug_work_func() local
60 struct drm_device *dev = adev->ddev; in amdgpu_hotplug_work_func()
83 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, in amdgpu_irq_reset_work_func() local
86 if (!amdgpu_sriov_vf(adev)) in amdgpu_irq_reset_work_func()
87 amdgpu_gpu_reset(adev); in amdgpu_irq_reset_work_func()
91 static void amdgpu_irq_disable_all(struct amdgpu_device *adev) in amdgpu_irq_disable_all() argument
97 spin_lock_irqsave(&adev->irq.lock, irqflags); in amdgpu_irq_disable_all()
99 if (!adev->irq.client[i].sources) in amdgpu_irq_disable_all()
103 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; in amdgpu_irq_disable_all()
110 r = src->funcs->set(adev, src, k, in amdgpu_irq_disable_all()
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| D | gmc_v7_0.c | 45 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
46 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
66 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) in gmc_v7_0_init_golden_registers() argument
68 switch (adev->asic_type) { in gmc_v7_0_init_golden_registers()
70 amdgpu_program_register_sequence(adev, in gmc_v7_0_init_golden_registers()
73 amdgpu_program_register_sequence(adev, in gmc_v7_0_init_golden_registers()
82 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev) in gmc_v7_0_mc_stop() argument
86 gmc_v7_0_wait_for_idle((void *)adev); in gmc_v7_0_mc_stop()
101 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev) in gmc_v7_0_mc_resume() argument
124 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) in gmc_v7_0_init_microcode() argument
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| D | gfx_v9_0.c | 180 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
181 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
182 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
183 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
184 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
186 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
187 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
190 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) in gfx_v9_0_init_golden_registers() argument
192 switch (adev->asic_type) { in gfx_v9_0_init_golden_registers()
194 amdgpu_program_register_sequence(adev, in gfx_v9_0_init_golden_registers()
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| D | amdgpu_kms.c | 49 struct amdgpu_device *adev = dev->dev_private; in amdgpu_driver_unload_kms() local
51 if (adev == NULL) in amdgpu_driver_unload_kms()
54 if (adev->rmmio == NULL) in amdgpu_driver_unload_kms()
57 if (amdgpu_sriov_vf(adev)) in amdgpu_driver_unload_kms()
58 amdgpu_virt_request_full_gpu(adev, false); in amdgpu_driver_unload_kms()
65 amdgpu_amdkfd_device_fini(adev); in amdgpu_driver_unload_kms()
67 amdgpu_acpi_fini(adev); in amdgpu_driver_unload_kms()
69 amdgpu_device_fini(adev); in amdgpu_driver_unload_kms()
72 kfree(adev); in amdgpu_driver_unload_kms()
87 struct amdgpu_device *adev; in amdgpu_driver_load_kms() local
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| D | amdgpu_bios.c | 89 static bool igp_read_bios_from_vram(struct amdgpu_device *adev) in igp_read_bios_from_vram() argument
95 if (!(adev->flags & AMD_IS_APU)) in igp_read_bios_from_vram()
96 if (amdgpu_need_post(adev)) in igp_read_bios_from_vram()
99 adev->bios = NULL; in igp_read_bios_from_vram()
100 vram_base = pci_resource_start(adev->pdev, 0); in igp_read_bios_from_vram()
106 adev->bios = kmalloc(size, GFP_KERNEL); in igp_read_bios_from_vram()
107 if (!adev->bios) { in igp_read_bios_from_vram()
111 adev->bios_size = size; in igp_read_bios_from_vram()
112 memcpy_fromio(adev->bios, bios, size); in igp_read_bios_from_vram()
115 if (!check_atom_bios(adev->bios, size)) { in igp_read_bios_from_vram()
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| D | gfx_v7_0.c | 54 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
55 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
56 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
881 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
882 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
883 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
884 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
885 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
899 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) in gfx_v7_0_init_microcode() argument
907 switch (adev->asic_type) { in gfx_v7_0_init_microcode()
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| D | vega10_ih.c | 38 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
47 static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) in vega10_ih_enable_interrupts() argument
54 adev->irq.ih.enabled = true; in vega10_ih_enable_interrupts()
64 static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) in vega10_ih_disable_interrupts() argument
74 adev->irq.ih.enabled = false; in vega10_ih_disable_interrupts()
75 adev->irq.ih.rptr = 0; in vega10_ih_disable_interrupts()
89 static int vega10_ih_irq_init(struct amdgpu_device *adev) in vega10_ih_irq_init() argument
98 vega10_ih_disable_interrupts(adev); in vega10_ih_irq_init()
100 if (adev->flags & AMD_IS_APU) in vega10_ih_irq_init()
101 nbio_v7_0_ih_control(adev); in vega10_ih_irq_init()
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| D | vce_v3_0.c | 64 static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx);
65 static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
66 static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
79 struct amdgpu_device *adev = ring->adev; in vce_v3_0_ring_get_rptr() local
82 mutex_lock(&adev->grbm_idx_mutex); in vce_v3_0_ring_get_rptr()
83 if (adev->vce.harvest_config == 0 || in vce_v3_0_ring_get_rptr()
84 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) in vce_v3_0_ring_get_rptr()
86 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) in vce_v3_0_ring_get_rptr()
89 if (ring == &adev->vce.ring[0]) in vce_v3_0_ring_get_rptr()
91 else if (ring == &adev->vce.ring[1]) in vce_v3_0_ring_get_rptr()
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| D | si.c | 902 static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg) in si_pcie_rreg() argument
907 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pcie_rreg()
911 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pcie_rreg()
915 static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in si_pcie_wreg() argument
919 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pcie_wreg()
924 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pcie_wreg()
927 static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) in si_pciep_rreg() argument
932 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pciep_rreg()
936 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pciep_rreg()
940 static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in si_pciep_wreg() argument
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| D | ci_dpm.c | 191 static u8 ci_get_memory_module_index(struct amdgpu_device *adev) in ci_get_memory_module_index() argument
201 static int ci_copy_and_switch_arb_sets(struct amdgpu_device *adev, in ci_copy_and_switch_arb_sets() argument
286 static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev, in ci_trim_voltage_table_to_fit_state_table() argument
303 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
306 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
307 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
309 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
310 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev);
311 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
313 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
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| D | gfx_v8_0.c | 653 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
654 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
655 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
656 static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
657 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
658 static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
662 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) in gfx_v8_0_init_golden_registers() argument
664 switch (adev->asic_type) { in gfx_v8_0_init_golden_registers()
666 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
669 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
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