| /drivers/clk/renesas/ |
| D | clk-div6.c | 49 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_enable() local
52 val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) in cpg_div6_clock_enable()
53 | CPG_DIV6_DIV(clock->div - 1); in cpg_div6_clock_enable()
54 clk_writel(val, clock->reg); in cpg_div6_clock_enable()
61 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_disable() local
64 val = clk_readl(clock->reg); in cpg_div6_clock_disable()
74 clk_writel(val, clock->reg); in cpg_div6_clock_disable()
79 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_is_enabled() local
81 return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP); in cpg_div6_clock_is_enabled()
87 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_recalc_rate() local
[all …]
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| D | rcar-gen3-cpg.c | 99 struct sd_clock *clock = to_sd_clock(hw); in cpg_sd_clock_enable() local
100 u32 val = readl(clock->reg); in cpg_sd_clock_enable()
103 val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK; in cpg_sd_clock_enable()
105 writel(val, clock->reg); in cpg_sd_clock_enable()
112 struct sd_clock *clock = to_sd_clock(hw); in cpg_sd_clock_disable() local
114 writel(readl(clock->reg) | CPG_SD_STP_MASK, clock->reg); in cpg_sd_clock_disable()
119 struct sd_clock *clock = to_sd_clock(hw); in cpg_sd_clock_is_enabled() local
121 return !(readl(clock->reg) & CPG_SD_STP_MASK); in cpg_sd_clock_is_enabled()
127 struct sd_clock *clock = to_sd_clock(hw); in cpg_sd_clock_recalc_rate() local
130 clock->div_table[clock->cur_div_idx].div); in cpg_sd_clock_recalc_rate()
[all …]
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| D | Kconfig | 2 bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
24 bool "Legacy DT clock support"
35 bool "Emma Mobile EV2 clock support" if COMPILE_TEST
38 bool "RZ/A1H clock support" if COMPILE_TEST
42 bool "R-Mobile APE6 clock support" if COMPILE_TEST
47 bool "R-Mobile A1 clock support" if COMPILE_TEST
52 bool "RZ/G1M clock support" if COMPILE_TEST
56 bool "RZ/G1E clock support" if COMPILE_TEST
60 bool "R-Car M1A clock support" if COMPILE_TEST
64 bool "R-Car H1 clock support" if COMPILE_TEST
[all …]
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| D | clk-mstp.c | 78 struct mstp_clock *clock = to_mstp_clock(hw); in cpg_mstp_clock_endisable() local
79 struct mstp_clock_group *group = clock->group; in cpg_mstp_clock_endisable()
80 u32 bitmask = BIT(clock->bit_index); in cpg_mstp_clock_endisable()
113 group->smstpcr, clock->bit_index); in cpg_mstp_clock_endisable()
132 struct mstp_clock *clock = to_mstp_clock(hw); in cpg_mstp_clock_is_enabled() local
133 struct mstp_clock_group *group = clock->group; in cpg_mstp_clock_is_enabled()
141 return !(value & BIT(clock->bit_index)); in cpg_mstp_clock_is_enabled()
155 struct mstp_clock *clock; in cpg_mstp_clock_register() local
158 clock = kzalloc(sizeof(*clock), GFP_KERNEL); in cpg_mstp_clock_register()
159 if (!clock) { in cpg_mstp_clock_register()
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| /drivers/soc/fsl/qe/ |
| D | ucc.c | 123 int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock, in ucc_set_qe_mux_rxtx() argument
143 switch (clock) { in ucc_set_qe_mux_rxtx()
158 switch (clock) { in ucc_set_qe_mux_rxtx()
173 switch (clock) { in ucc_set_qe_mux_rxtx()
189 switch (clock) { in ucc_set_qe_mux_rxtx()
220 static int ucc_get_tdm_common_clk(u32 tdm_num, enum qe_clock clock) in ucc_get_tdm_common_clk() argument
235 switch (clock) { in ucc_get_tdm_common_clk()
256 switch (clock) { in ucc_get_tdm_common_clk()
280 static int ucc_get_tdm_rx_clk(u32 tdm_num, enum qe_clock clock) in ucc_get_tdm_rx_clk() argument
286 switch (clock) { in ucc_get_tdm_rx_clk()
[all …]
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| /drivers/gpu/drm/gma500/ |
| D | cdv_intel_display.c | 223 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select) in cdv_dpll_set_clock_cdv() argument
281 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
297 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
299 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
302 } else if (clock->vco < 2750000) { in cdv_dpll_set_clock_cdv()
305 } else if (clock->vco < 3300000) { in cdv_dpll_set_clock_cdv()
321 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); in cdv_dpll_set_clock_cdv()
322 switch (clock->p2) { in cdv_dpll_set_clock_cdv()
336 DRM_ERROR("Bad P2 clock: %d\n", clock->p2); in cdv_dpll_set_clock_cdv()
402 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) in cdv_intel_clock() argument
[all …]
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| D | oaktrail_crtc.c | 121 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) in mrst_lvds_clock() argument
123 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
126 static void mrst_print_pll(struct gma_clock_t *clock) in mrst_print_pll() argument
129 clock->dot, clock->m, clock->m1, clock->m2, clock->n, in mrst_print_pll()
130 clock->p1, clock->p2); in mrst_print_pll()
137 struct gma_clock_t clock; in mrst_sdvo_find_best_pll() local
142 memset(&clock, 0, sizeof(clock)); in mrst_sdvo_find_best_pll()
144 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { in mrst_sdvo_find_best_pll()
145 for (clock.n = limit->n.min; clock.n <= limit->n.max; in mrst_sdvo_find_best_pll()
146 clock.n++) { in mrst_sdvo_find_best_pll()
[all …]
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| D | psb_intel_display.c | 77 static void psb_intel_clock(int refclk, struct gma_clock_t *clock) in psb_intel_clock() argument
79 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in psb_intel_clock()
80 clock->p = clock->p1 * clock->p2; in psb_intel_clock()
81 clock->vco = refclk * clock->m / (clock->n + 2); in psb_intel_clock()
82 clock->dot = clock->vco / clock->p; in psb_intel_clock()
115 struct gma_clock_t clock; in psb_intel_crtc_mode_set() local
153 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, in psb_intel_crtc_mode_set()
154 &clock); in psb_intel_crtc_mode_set()
157 adjusted_mode->clock, clock.dot); in psb_intel_crtc_mode_set()
161 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; in psb_intel_crtc_mode_set()
[all …]
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| D | gma_display.c | 674 struct gma_clock_t *clock) in gma_pll_is_valid() argument
676 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in gma_pll_is_valid()
678 if (clock->p < limit->p.min || limit->p.max < clock->p) in gma_pll_is_valid()
680 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in gma_pll_is_valid()
682 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in gma_pll_is_valid()
685 if (clock->m1 <= clock->m2 && clock->m1 != 0) in gma_pll_is_valid()
687 if (clock->m < limit->m.min || limit->m.max < clock->m) in gma_pll_is_valid()
689 if (clock->n < limit->n.min || limit->n.max < clock->n) in gma_pll_is_valid()
691 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in gma_pll_is_valid()
697 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) in gma_pll_is_valid()
[all …]
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| /drivers/net/phy/ |
| D | dp83640.c | 112 struct dp83640_clock *clock; member
235 if (dp83640->clock->page != page) { in ext_read()
237 dp83640->clock->page = page; in ext_read()
250 if (dp83640->clock->page != page) { in ext_write()
252 dp83640->clock->page = page; in ext_write()
307 static int periodic_output(struct dp83640_clock *clock, in periodic_output() argument
311 struct dp83640_private *dp83640 = clock->chosen; in periodic_output()
317 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, in periodic_output()
335 mutex_lock(&clock->extreg_lock); in periodic_output()
338 mutex_unlock(&clock->extreg_lock); in periodic_output()
[all …]
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| /drivers/video/fbdev/via/ |
| D | via_clock.c | 297 void via_clock_init(struct via_clock *clock, int gfx_chip) in via_clock_init() argument
302 clock->set_primary_clock_state = dummy_set_clock_state; in via_clock_init()
303 clock->set_primary_clock_source = dummy_set_clock_source; in via_clock_init()
304 clock->set_primary_pll_state = dummy_set_pll_state; in via_clock_init()
305 clock->set_primary_pll = cle266_set_primary_pll; in via_clock_init()
307 clock->set_secondary_clock_state = dummy_set_clock_state; in via_clock_init()
308 clock->set_secondary_clock_source = dummy_set_clock_source; in via_clock_init()
309 clock->set_secondary_pll_state = dummy_set_pll_state; in via_clock_init()
310 clock->set_secondary_pll = cle266_set_secondary_pll; in via_clock_init()
312 clock->set_engine_pll_state = dummy_set_pll_state; in via_clock_init()
[all …]
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| /drivers/clk/bcm/ |
| D | Kconfig | 2 bool "Broadcom BCM63xx clock support"
7 Enable common clock framework support for Broadcom BCM63xx DSL SoCs
11 bool "Broadcom Kona CCU clock support"
15 Enable common clock framework support for Broadcom SoCs
16 using "Kona" style clock control units, including those
22 Enable common clock framework support for Broadcom SoCs
26 bool "Broadcom Cygnus clock support"
31 Enable common clock framework support for the Broadcom Cygnus SoC
34 bool "Broadcom Northstar/Northstar Plus clock support"
39 Enable common clock framework support for the Broadcom Northstar and
[all …]
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| /drivers/clk/ti/ |
| D | adpll.c | 212 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, in ti_adpll_setup_clock() argument
220 d->clocks[index].clk = clock; in ti_adpll_setup_clock()
230 cl = clkdev_create(clock, con_id, NULL); in ti_adpll_setup_clock()
241 d->outputs.clks[output_index] = clock; in ti_adpll_setup_clock()
257 struct clk *clock; in ti_adpll_init_divider() local
264 clock = clk_register_divider(d->dev, child_name, parent_name, 0, in ti_adpll_init_divider()
267 if (IS_ERR(clock)) { in ti_adpll_init_divider()
269 name, PTR_ERR(clock)); in ti_adpll_init_divider()
270 return PTR_ERR(clock); in ti_adpll_init_divider()
273 return ti_adpll_setup_clock(d, clock, index, output_index, child_name, in ti_adpll_init_divider()
[all …]
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| /drivers/media/platform/qcom/camss-8x16/ |
| D | camss-csiphy.c | 176 struct camss_clock *clock = &csiphy->clock[i]; in csiphy_set_clock_rates() local
178 if (!strcmp(clock->name, "csiphy0_timer") || in csiphy_set_clock_rates()
179 !strcmp(clock->name, "csiphy1_timer")) { in csiphy_set_clock_rates()
188 for (j = 0; j < clock->nfreqs; j++) in csiphy_set_clock_rates()
189 if (min_rate < clock->freq[j]) in csiphy_set_clock_rates()
192 if (j == clock->nfreqs) { in csiphy_set_clock_rates()
201 j = clock->nfreqs - 1; in csiphy_set_clock_rates()
203 round_rate = clk_round_rate(clock->clk, clock->freq[j]); in csiphy_set_clock_rates()
212 ret = clk_set_rate(clock->clk, csiphy->timer_clk_rate); in csiphy_set_clock_rates()
254 ret = camss_enable_clocks(csiphy->nclocks, csiphy->clock, dev); in csiphy_set_power()
[all …]
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| D | camss-csid.c | 240 struct camss_clock *clock = &csid->clock[i]; in csid_set_clock_rates() local
242 if (!strcmp(clock->name, "csi0") || in csid_set_clock_rates()
243 !strcmp(clock->name, "csi1")) { in csid_set_clock_rates()
252 for (j = 0; j < clock->nfreqs; j++) in csid_set_clock_rates()
253 if (min_rate < clock->freq[j]) in csid_set_clock_rates()
256 if (j == clock->nfreqs) { in csid_set_clock_rates()
265 j = clock->nfreqs - 1; in csid_set_clock_rates()
267 rate = clk_round_rate(clock->clk, clock->freq[j]); in csid_set_clock_rates()
274 ret = clk_set_rate(clock->clk, rate); in csid_set_clock_rates()
336 ret = camss_enable_clocks(csid->nclocks, csid->clock, dev); in csid_set_power()
[all …]
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| /drivers/ptp/ |
| D | Kconfig | 2 # PTP clock support configuration
5 menu "PTP clock support"
8 tristate "PTP clock support"
22 devices. If you want to use a PTP clock, then you should
23 also enable at least one clock driver as well.
29 tristate "Broadcom DTE as PTP clock"
36 (DTE) in the Broadcom SoC's as a PTP clock.
38 The clock can be used in both wired and wireless networks
45 tristate "Freescale eTSEC as PTP clock"
51 clock. This clock is only useful if your PTP programs are
[all …]
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| /drivers/clocksource/ |
| D | clps711x-timer.c | 34 static int __init _clps711x_clksrc_init(struct clk *clock, void __iomem *base) in _clps711x_clksrc_init() argument
40 if (IS_ERR(clock)) in _clps711x_clksrc_init()
41 return PTR_ERR(clock); in _clps711x_clksrc_init()
43 rate = clk_get_rate(clock); in _clps711x_clksrc_init()
64 static int __init _clps711x_clkevt_init(struct clk *clock, void __iomem *base, in _clps711x_clkevt_init() argument
74 if (IS_ERR(clock)) in _clps711x_clkevt_init()
75 return PTR_ERR(clock); in _clps711x_clkevt_init()
81 rate = clk_get_rate(clock); in _clps711x_clkevt_init()
110 struct clk *clock = of_clk_get(np, 0); in clps711x_timer_init() local
115 return _clps711x_clksrc_init(clock, base); in clps711x_timer_init()
[all …]
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| /drivers/gpu/drm/mgag200/ |
| D | mgag200_mode.c | 103 static int mga_g200se_set_plls(struct mga_device *mdev, long clock) in mga_g200se_set_plls() argument
122 permitteddelta = clock * 5 / 1000; in mga_g200se_set_plls()
125 if (clock * testp > vcomax) in mga_g200se_set_plls()
127 if (clock * testp < vcomin) in mga_g200se_set_plls()
134 if (computed > clock) in mga_g200se_set_plls()
135 tmpdelta = computed - clock; in mga_g200se_set_plls()
137 tmpdelta = clock - computed; in mga_g200se_set_plls()
155 if (clock < 25000) in mga_g200se_set_plls()
156 clock = 25000; in mga_g200se_set_plls()
158 clock = clock * 2; in mga_g200se_set_plls()
[all …]
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| /drivers/clk/ |
| D | Kconfig | 16 The common clock framework is a single definition of struct
18 implementation of the clock API in include/linux/clk.h.
46 clock.
52 This driver supports RK805, RK808 and RK818 crystal oscillator clock. These
61 This driver supports the hi655x PMIC clock. This
73 firmware providing all the clock controls.
81 This driver supports Silicon Labs 5351A/B/C programmable clock
91 This driver supports the Silicon Labs 514 programmable clock
102 clock generators.
105 tristate "Clock driver for TI CDCE706 clock synthesizer"
[all …]
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| /drivers/clk/samsung/ |
| D | Kconfig | 3 bool "Samsung Exynos clock controller support" if COMPILE_TEST
9 bool "Samsung Exynos ARMv8-family clock controller support" if COMPILE_TEST
13 tristate "Samsung Exynos AUDSS clock controller support"
17 Support for the Audio Subsystem CLKCON clock controller present
23 bool "Samsung S3C2410 clock controller support" if COMPILE_TEST
26 Build the s3c2410 clock driver based on the common clock framework.
33 Temporary symbol to build the dclk driver based on the common clock
37 bool "Samsung S3C2412 clock controller support" if COMPILE_TEST
41 bool "Samsung S3C2443 clock controller support" if COMPILE_TEST
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| /drivers/staging/clocking-wizard/ |
| D | dt-binding.txt | 3 This binding uses the common clock binding[1]. Details about the devices can be
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 - clocks: Handle to input clock
14 - clock-names: Tuple containing 'clk_in1' and 's_axi_aclk'
15 - clock-output-names: Names for the output clocks
21 clock-generator@40040000 {
25 clock-names = "clk_in1", "s_axi_aclk";
27 clock-output-names = "clk_out0", "clk_out1", "clk_out2",
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_afmt.c | 51 static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) in amdgpu_afmt_calc_cts() argument
58 cts = clock * 1000; in amdgpu_afmt_calc_cts()
88 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock) in amdgpu_afmt_acr() argument
95 if (amdgpu_afmt_predefined_acr[i].clock == clock) in amdgpu_afmt_acr()
100 amdgpu_afmt_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000); in amdgpu_afmt_acr()
101 amdgpu_afmt_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100); in amdgpu_afmt_acr()
102 amdgpu_afmt_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000); in amdgpu_afmt_acr()
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| /drivers/gpu/drm/panel/ |
| D | panel-simple.c | 392 .clock = 9000,
417 .clock = 33333,
442 .clock = 51450,
465 .clock = 72500,
488 .clock = 72000,
512 .clock = 70589,
535 .clock = 69500,
558 .clock = 150660,
672 .clock = 148800,
699 .clock = 51200,
[all …]
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| /drivers/mfd/ |
| D | db8500-prcmu.c | 1120 static int request_pll(u8 clock, bool enable) in request_pll() argument
1124 if (clock == PRCMU_PLLSOC0) in request_pll()
1125 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); in request_pll()
1126 else if (clock == PRCMU_PLLSOC1) in request_pll()
1127 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); in request_pll()
1137 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); in request_pll()
1319 static int request_clock(u8 clock, bool enable) in request_clock() argument
1330 val = readl(prcmu_base + clk_mgt[clock].offset); in request_clock()
1332 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); in request_clock()
1334 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); in request_clock()
[all …]
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| /drivers/clk/qcom/ |
| D | Kconfig | 9 tristate "Support for Qualcomm's clock controllers"
23 memory and accepts clock requests, aggregates the requests and turns
36 memory and accepts clock requests, aggregates the requests and turns
46 Support for the global clock controller on apq8084 devices.
56 Support for the multimedia clock controller on apq8084 devices.
64 Support for the global clock controller on ipq4019 devices.
72 Support for the global clock controller on ipq806x devices.
81 Support for the LPASS clock controller on ipq806x devices.
89 Support for global clock controller on ipq8074 devices.
91 i2c, USB, SD/eMMC, etc. Select this for the root clock
[all …]
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