Home
last modified time | relevance | path

Searched refs:dpm_table (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/powerplay/hwmgr/
Dvega10_hwmgr.c1196 struct vega10_single_dpm_table *dpm_table, in vega10_setup_default_single_dpm_table() argument
1202 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= in vega10_setup_default_single_dpm_table()
1204 dpm_table->dpm_levels[dpm_table->count].value = in vega10_setup_default_single_dpm_table()
1206 dpm_table->dpm_levels[dpm_table->count].enabled = true; in vega10_setup_default_single_dpm_table()
1207 dpm_table->count++; in vega10_setup_default_single_dpm_table()
1215 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table); in vega10_setup_default_pcie_table()
1267 struct vega10_single_dpm_table *dpm_table; in vega10_setup_default_dpm_tables() local
1309 data->dpm_table.soc_table.count = 0; in vega10_setup_default_dpm_tables()
1310 data->dpm_table.gfx_table.count = 0; in vega10_setup_default_dpm_tables()
1311 data->dpm_table.dcef_table.count = 0; in vega10_setup_default_dpm_tables()
[all …]
Dsmu7_hwmgr.c555 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, in smu7_setup_default_pcie_table()
566 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, in smu7_setup_default_pcie_table()
572 data->dpm_table.pcie_speed_table.count = max_entry - 1; in smu7_setup_default_pcie_table()
576 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, in smu7_setup_default_pcie_table()
581 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, in smu7_setup_default_pcie_table()
586 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, in smu7_setup_default_pcie_table()
591 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, in smu7_setup_default_pcie_table()
596 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, in smu7_setup_default_pcie_table()
601 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, in smu7_setup_default_pcie_table()
607 data->dpm_table.pcie_speed_table.count = 6; in smu7_setup_default_pcie_table()
[all …]
Dhwmgr.c472 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_reset_single_dpm_table() local
474 dpm_table->count = count > max ? max : count; in phm_reset_single_dpm_table()
476 for (i = 0; i < dpm_table->count; i++) in phm_reset_single_dpm_table()
477 dpm_table->dpm_level[i].enabled = false; in phm_reset_single_dpm_table()
487 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_setup_pcie_table_entry() local
488 dpm_table->dpm_level[index].value = pcie_gen; in phm_setup_pcie_table_entry()
489 dpm_table->dpm_level[index].param1 = pcie_lanes; in phm_setup_pcie_table_entry()
490 dpm_table->dpm_level[index].enabled = 1; in phm_setup_pcie_table_entry()
497 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_get_dpm_level_enable_mask_value() local
499 for (i = dpm_table->count; i > 0; i--) { in phm_get_dpm_level_enable_mask_value()
[all …]
Dsmu7_hwmgr.h182 struct smu7_dpm_table dpm_table; member
Dvega10_hwmgr.h310 struct vega10_dpm_table dpm_table; member
/drivers/gpu/drm/amd/powerplay/smumgr/
Dfiji_smc.c222 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in fiji_populate_bapm_parameters_in_dpm_table() local
234 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
236 dpm_table->TargetTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
243 dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp); in fiji_populate_bapm_parameters_in_dpm_table()
244 dpm_table->GpuTjHyst = 8; in fiji_populate_bapm_parameters_in_dpm_table()
246 dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase; in fiji_populate_bapm_parameters_in_dpm_table()
249 dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
251 dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
253 dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
255 dpm_table->TemperatureLimitLiquid2 = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
[all …]
Diceland_smc.c603 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_smc_link_level() local
608 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in iceland_populate_smc_link_level()
610 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in iceland_populate_smc_link_level()
612 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in iceland_populate_smc_link_level()
624 (uint8_t)dpm_table->pcie_speed_table.count; in iceland_populate_smc_link_level()
626 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in iceland_populate_smc_link_level()
820 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_all_graphic_levels() local
837 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
839 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
854 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels()
[all …]
Dtonga_smc.c408 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_smc_link_level() local
413 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in tonga_populate_smc_link_level()
415 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in tonga_populate_smc_link_level()
417 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in tonga_populate_smc_link_level()
429 (uint8_t)dpm_table->pcie_speed_table.count; in tonga_populate_smc_link_level()
431 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in tonga_populate_smc_link_level()
603 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_all_graphic_levels() local
605 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count; in tonga_populate_all_graphic_levels()
622 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
624 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
[all …]
Dpolaris10_smc.c529 struct smu7_dpm_table *dpm_table = &data->dpm_table; in polaris10_populate_smc_link_level() local
534 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in polaris10_populate_smc_link_level()
536 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in polaris10_populate_smc_link_level()
538 dpm_table->pcie_speed_table.dpm_levels[i].param1); in polaris10_populate_smc_link_level()
546 (uint8_t)dpm_table->pcie_speed_table.count; in polaris10_populate_smc_link_level()
550 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in polaris10_populate_smc_link_level()
757 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in polaris10_populate_all_graphic_levels() local
761 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in polaris10_populate_all_graphic_levels()
777 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels()
780 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
[all …]
/drivers/gpu/drm/radeon/
Dci_dpm.c432 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table() local
440 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
441 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
443 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
444 dpm_table->GpuTjMax = in ci_populate_bapm_parameters_in_dpm_table()
446 dpm_table->GpuTjHyst = 8; in ci_populate_bapm_parameters_in_dpm_table()
448 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; in ci_populate_bapm_parameters_in_dpm_table()
451 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); in ci_populate_bapm_parameters_in_dpm_table()
452 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); in ci_populate_bapm_parameters_in_dpm_table()
454 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
[all …]
Dci_dpm.h194 struct ci_dpm_table dpm_table; member
/drivers/gpu/drm/amd/amdgpu/
Dci_dpm.c557 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table() local
565 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
566 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
568 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
569 dpm_table->GpuTjMax = in ci_populate_bapm_parameters_in_dpm_table()
571 dpm_table->GpuTjHyst = 8; in ci_populate_bapm_parameters_in_dpm_table()
573 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; in ci_populate_bapm_parameters_in_dpm_table()
576 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); in ci_populate_bapm_parameters_in_dpm_table()
577 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); in ci_populate_bapm_parameters_in_dpm_table()
579 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
[all …]
Dci_dpm.h195 struct ci_dpm_table dpm_table; member