| /drivers/gpu/drm/radeon/ |
| D | trinity_dpm.c | 993 if ((old_rps->evclk != new_rps->evclk) || in trinity_set_vce_clock()
996 if (new_rps->evclk || new_rps->ecclk) in trinity_set_vce_clock()
1000 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in trinity_set_vce_clock()
1504 u32 evclk, u32 ecclk, u16 *voltage) in trinity_get_vce_clock_voltage() argument
1511 if (((evclk == 0) && (ecclk == 0)) || in trinity_get_vce_clock_voltage()
1518 if ((evclk <= table->entries[i].evclk) && in trinity_get_vce_clock_voltage()
1554 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in trinity_apply_state_adjust_rules()
1557 new_rps->evclk = 0; in trinity_apply_state_adjust_rules()
1575 trinity_get_vce_clock_voltage(rdev, new_rps->evclk, new_rps->ecclk, &min_vce_voltage); in trinity_apply_state_adjust_rules()
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| D | kv_dpm.c | 906 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); in kv_populate_vce_table()
910 (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk); in kv_populate_vce_table()
913 table->entries[i].evclk, false, ÷rs); in kv_populate_vce_table()
1459 static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk) in kv_get_vce_boot_level() argument
1466 if (table->entries[i].evclk >= evclk) in kv_get_vce_boot_level()
1482 if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) { in kv_update_vce_dpm()
1489 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk); in kv_update_vce_dpm()
1506 } else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) { in kv_update_vce_dpm()
2154 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in kv_apply_state_adjust_rules()
2157 new_rps->evclk = 0; in kv_apply_state_adjust_rules()
[all …]
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| D | radeon_asic.h | 698 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
750 int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
788 int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
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| D | si_dpm.c | 2935 u32 evclk, u32 ecclk, u16 *voltage) in si_get_vce_clock_voltage() argument
2942 if (((evclk == 0) && (ecclk == 0)) || in si_get_vce_clock_voltage()
2949 if ((evclk <= table->entries[i].evclk) && in si_get_vce_clock_voltage()
3006 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in si_apply_state_adjust_rules()
3008 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
3011 rps->evclk = 0; in si_apply_state_adjust_rules()
5931 if ((old_rps->evclk != new_rps->evclk) || in si_set_vce_clock()
5934 if (new_rps->evclk || new_rps->ecclk) in si_set_vce_clock()
5938 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in si_set_vce_clock()
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| D | radeon.h | 1349 u32 evclk; member
1444 u32 evclk; member
1533 u32 evclk; member
1965 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
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| D | ci_dpm.c | 803 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in ci_apply_state_adjust_rules()
806 rps->evclk = 0; in ci_apply_state_adjust_rules()
2679 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; in ci_populate_smc_vce_level()
4083 if (table->entries[i].evclk >= min_evclk) in ci_get_vce_boot_level()
4098 if (radeon_current_state->evclk != radeon_new_state->evclk) { in ci_update_vce_dpm()
4099 if (radeon_new_state->evclk) { in ci_update_vce_dpm()
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| D | r600_dpm.c | 1108 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = in r600_parse_extended_power_table()
1123 rdev->pm.dpm.vce_states[i].evclk = in r600_parse_extended_power_table()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | kv_dpm.c | 992 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); in kv_populate_vce_table()
996 (u8)kv_get_clk_bypass(adev, table->entries[i].evclk); in kv_populate_vce_table()
999 table->entries[i].evclk, false, ÷rs); in kv_populate_vce_table()
1526 static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk) in kv_get_vce_boot_level() argument
1533 if (table->entries[i].evclk >= evclk) in kv_get_vce_boot_level()
1549 if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) { in kv_update_vce_dpm()
1554 pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk); in kv_update_vce_dpm()
1570 } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) { in kv_update_vce_dpm()
2207 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in kv_apply_state_adjust_rules()
2210 new_rps->evclk = 0; in kv_apply_state_adjust_rules()
[all …]
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| D | amdgpu_dpm.h | 65 u32 evclk; member
162 u32 evclk; member
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| D | amdgpu_dpm.c | 549 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = in amdgpu_parse_extended_power_table()
565 adev->pm.dpm.vce_states[i].evclk = in amdgpu_parse_extended_power_table()
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| D | si_dpm.c | 3033 u32 evclk, u32 ecclk, u16 *voltage) in si_get_vce_clock_voltage() argument
3040 if (((evclk == 0) && (ecclk == 0)) || in si_get_vce_clock_voltage()
3047 if ((evclk <= table->entries[i].evclk) && in si_get_vce_clock_voltage()
3464 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in si_apply_state_adjust_rules()
3466 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
3469 rps->evclk = 0; in si_apply_state_adjust_rules()
7961 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); in si_check_state_equal()
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| D | ci_dpm.c | 933 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in ci_apply_state_adjust_rules()
936 rps->evclk = 0; in ci_apply_state_adjust_rules()
2831 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; in ci_populate_smc_vce_level()
4286 if (table->entries[i].evclk >= min_evclk) in ci_get_vce_boot_level()
4301 if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) { in ci_update_vce_dpm()
4302 if (amdgpu_new_state->evclk) { in ci_update_vce_dpm()
6197 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); in ci_check_state_equal()
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| D | soc15.c | 467 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in soc15_set_vce_clocks() argument
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| D | cik.c | 1261 static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in cik_set_vce_clocks() argument
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| D | amdgpu_kms.c | 607 vce_clk_table.entries[i].eclk = vce_state->evclk; in amdgpu_info_ioctl()
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| /drivers/gpu/drm/amd/powerplay/inc/ |
| D | power_state.h | 173 unsigned long evclk; member
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| D | hwmgr.h | 136 uint32_t evclk; member
188 uint32_t evclk; member
255 uint32_t evclk; member
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| /drivers/gpu/drm/amd/include/ |
| D | amd_shared.h | 106 u32 evclk; member
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| /drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | rv_hwmgr.h | 131 uint32_t evclk; member
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| D | smu7_hwmgr.h | 78 uint32_t evclk; member
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| D | cz_hwmgr.h | 151 uint32_t evclk; member
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| D | vega10_hwmgr.h | 101 uint32_t evclk; member
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| D | cz_hwmgr.c | 1113 cz_ps->evclk = hwmgr->vce_arbiter.evclk; in cz_apply_state_adjust_rules()
1119 hwmgr->vce_arbiter.evclk != 0 || hwmgr->vce_arbiter.ecclk != 0); in cz_apply_state_adjust_rules()
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| D | processpptables.c | 1104 vce_table->entries[i].evclk = ((unsigned long)entry->ucEVClkHigh << 16) in get_vce_clock_voltage_limit_table()
1552 vce_state->evclk = ((uint32_t)vce_clock_info->ucEVClkHigh << 16) | vce_clock_info->usEVClkLow; in get_vce_state_table_entry()
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| D | smu7_hwmgr.c | 2722 smu7_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk; in smu7_apply_state_adjust_rules()
4087 …*equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.e… in smu7_check_states_equal()
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